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ef50d6c06e
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
145 lines
4.3 KiB
C
145 lines
4.3 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc_asm.tmpl>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* --------------------------------------------------------------- */
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void get_sys_info (sys_info_t * sysInfo)
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{
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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uint plat_ratio,e500_ratio,half_freqSystemBus;
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plat_ratio = (gur->porpllsr) & 0x0000003e;
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plat_ratio >>= 1;
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sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
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e500_ratio = (gur->porpllsr) & 0x003f0000;
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e500_ratio >>= 16;
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/* Divide before multiply to avoid integer
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* overflow for processor speeds above 2GHz */
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half_freqSystemBus = sysInfo->freqSystemBus/2;
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sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
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/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
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sysInfo->freqDDRBus = sysInfo->freqSystemBus;
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#ifdef CONFIG_DDR_CLK_FREQ
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{
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u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
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if (ddr_ratio != 0x7)
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sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
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}
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#endif
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}
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int get_clocks (void)
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{
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sys_info_t sys_info;
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#ifdef CONFIG_MPC8544
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volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
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#endif
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#if defined(CONFIG_CPM2)
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
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uint sccr, dfbrg;
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/* set VCO = 4 * BRG */
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cpm->im_cpm_intctl.sccr &= 0xfffffffc;
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sccr = cpm->im_cpm_intctl.sccr;
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dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
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#endif
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get_sys_info (&sys_info);
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gd->cpu_clk = sys_info.freqProcessor;
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gd->bus_clk = sys_info.freqSystemBus;
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gd->mem_clk = sys_info.freqDDRBus;
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/*
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* The base clock for I2C depends on the actual SOC. Unfortunately,
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* there is no pattern that can be used to determine the frequency, so
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* the only choice is to look up the actual SOC number and use the value
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* for that SOC. This information is taken from application note
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* AN2919.
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*/
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#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
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gd->i2c1_clk = sys_info.freqSystemBus;
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#elif defined(CONFIG_MPC8544)
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/*
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* On the 8544, the I2C clock is the same as the SEC clock. This can be
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* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
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* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
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* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
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* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
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*/
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if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
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gd->i2c1_clk = sys_info.freqSystemBus / 3;
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else
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gd->i2c1_clk = sys_info.freqSystemBus / 2;
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#else
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/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
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gd->i2c1_clk = sys_info.freqSystemBus / 2;
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#endif
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gd->i2c2_clk = gd->i2c1_clk;
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#if defined(CONFIG_MPC8536)
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gd->sdhc_clk = gd->bus_clk / 2;
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#endif
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#if defined(CONFIG_CPM2)
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gd->vco_out = 2*sys_info.freqSystemBus;
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gd->cpm_clk = gd->vco_out / 2;
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gd->scc_clk = gd->vco_out / 4;
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gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
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#endif
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if(gd->cpu_clk != 0) return (0);
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else return (1);
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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*********************************************/
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ulong get_bus_freq (ulong dummy)
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{
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return gd->bus_clk;
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}
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/********************************************
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* get_ddr_freq
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* return ddr bus freq in Hz
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*********************************************/
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ulong get_ddr_freq (ulong dummy)
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{
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return gd->mem_clk;
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}
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