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601 lines
15 KiB
ArmAsm
601 lines
15 KiB
ArmAsm
/*This file is subject to the terms and conditions of the GNU General Public
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* License.
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*
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* Blackfin BF533/2.6 support : LG Soft India
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* Modification: Dec 07 2004
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* 1. Correction in icheck_lock. Valid lock entries were
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* geting victimized, for instruction cplb replacement.
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* 2. Setup loop's are modified as now toolchain support's P Indexed
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* addressing
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* :LG Soft India
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*
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*/
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/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
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* is_data_miss==2 => Mark as Dirty, write to the clean data page
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* is_data_miss==1 => Replace a data CPLB.
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* is_data_miss==0 => Replace an instruction CPLB.
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*
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* Returns:
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* CPLB_RELOADED => Successfully updated CPLB table.
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* CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.This indicates
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* that the CPLBs in the configuration tablei are badly
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* configured, as this should never occur.
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* CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the exception,
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* is not covered by any of the CPLBs in the configuration
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* table. The application isi presumably misbehaving.
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* CPLB_PROT_VIOL => The address being accessed, that triggered thei exception,
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* was not a first-write to a clean Write Back Data page,
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* and so presumably is a genuine violation of the page's
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* protection attributes. The application is misbehaving.
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*/
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#define ASSEMBLY
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#include <asm-blackfin/linkage.h>
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#include <asm-blackfin/blackfin.h>
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#include <asm-blackfin/cplbtab.h>
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#include <asm-blackfin/cplb.h>
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.text
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.align 2;
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ENTRY(_cplb_mgr)
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[--SP]=( R7:0,P5:0 );
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CC = R0 == 2;
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IF CC JUMP dcplb_write;
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CC = R0 == 0;
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IF !CC JUMP dcplb_miss_compare;
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/* ICPLB Miss Exception. We need to choose one of the
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* currently-installed CPLBs, and replace it with one
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* from the configuration table.
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*/
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P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
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P4.H = (ICPLB_FAULT_ADDR >> 16);
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P1 = 16;
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P5.L = page_size_table;
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P5.H = page_size_table;
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P0.L = (ICPLB_DATA0 & 0xFFFF);
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P0.H = (ICPLB_DATA0 >> 16);
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R4 = [P4]; /* Get faulting address*/
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R6 = 64; /* Advance past the fault address, which*/
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R6 = R6 + R4; /* we'll use if we find a match*/
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R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/
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R5 = 0;
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isearch:
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R1 = [P0-0x100]; /* Address for this CPLB */
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R0 = [P0++]; /* Info for this CPLB*/
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CC = BITTST(R0,0); /* Is the CPLB valid?*/
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IF !CC JUMP nomatch; /* Skip it, if not.*/
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CC = R4 < R1(IU); /* If fault address less than page start*/
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IF CC JUMP nomatch; /* then skip this one.*/
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R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/
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P1 = R2;
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P1 = P5 + (P1<<2); /* index into page-size table*/
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R2 = [P1]; /* Get the page size*/
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R1 = R1 + R2; /* and add to page start, to get page end*/
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CC = R4 < R1(IU); /* and see whether fault addr is in page.*/
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IF !CC R4 = R6; /* If so, advance the address and finish loop.*/
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IF !CC JUMP isearch_done;
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nomatch:
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/* Go around again*/
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R5 += 1;
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CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
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IF !CC JUMP isearch;
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isearch_done:
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I0 = R4; /* Fault address we'll search for*/
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/* set up pointers */
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P0.L = (ICPLB_DATA0 & 0xFFFF);
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P0.H = (ICPLB_DATA0 >> 16);
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/* The replacement procedure for ICPLBs */
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P4.L = (IMEM_CONTROL & 0xFFFF);
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P4.H = (IMEM_CONTROL >> 16);
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/* disable cplbs */
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R5 = [P4]; /* Control Register*/
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BITCLR(R5,ENICPLB_P);
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CLI R1;
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SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
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.align 8;
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[P4] = R5;
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SSYNC;
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STI R1;
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R1 = -1; /* end point comparison */
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R3 = 16; /* counter */
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/* Search through CPLBs for first non-locked entry */
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/* Overwrite it by moving everyone else up by 1 */
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icheck_lock:
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R0 = [P0++];
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R3 = R3 + R1;
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CC = R3 == R1;
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IF CC JUMP all_locked;
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CC = BITTST(R0, 0); /* an invalid entry is good */
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IF !CC JUMP ifound_victim;
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CC = BITTST(R0,1); /* but a locked entry isn't */
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IF CC JUMP icheck_lock;
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ifound_victim:
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#ifdef CONFIG_CPLB_INFO
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R7 = [P0 - 0x104];
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P2.L = ipdt_table;
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P2.H = ipdt_table;
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P3.L = ipdt_swapcount_table;
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P3.H = ipdt_swapcount_table;
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P3 += -4;
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icount:
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R2 = [P2]; /* address from config table */
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P2 += 8;
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P3 += 8;
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CC = R2==-1;
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IF CC JUMP icount_done;
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CC = R7==R2;
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IF !CC JUMP icount;
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R7 = [P3];
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R7 += 1;
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[P3] = R7;
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CSYNC;
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icount_done:
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#endif
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LC0=R3;
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LSETUP(is_move,ie_move) LC0;
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is_move:
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R0 = [P0];
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[P0 - 4] = R0;
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R0 = [P0 - 0x100];
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[P0-0x104] = R0;
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ie_move:P0+=4;
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/* We've made space in the ICPLB table, so that ICPLB15
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* is now free to be overwritten. Next, we have to determine
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* which CPLB we need to install, from the configuration
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* table. This is a matter of getting the start-of-page
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* addresses and page-lengths from the config table, and
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* determining whether the fault address falls within that
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* range.
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*/
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P2.L = ipdt_table;
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P2.H = ipdt_table;
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#ifdef CONFIG_CPLB_INFO
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P3.L = ipdt_swapcount_table;
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P3.H = ipdt_swapcount_table;
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P3 += -8;
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#endif
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P0.L = page_size_table;
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P0.H = page_size_table;
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/* Retrieve our fault address (which may have been advanced
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* because the faulting instruction crossed a page boundary).
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*/
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R0 = I0;
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/* An extraction pattern, to get the page-size bits from
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* the CPLB data entry. Bits 16-17, so two bits at posn 16.
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*/
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R1 = ((16<<8)|2);
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inext: R4 = [P2++]; /* address from config table */
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R2 = [P2++]; /* data from config table */
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#ifdef CONFIG_CPLB_INFO
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P3 += 8;
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#endif
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CC = R4 == -1; /* End of config table*/
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IF CC JUMP no_page_in_table;
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/* See if failed address > start address */
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CC = R4 <= R0(IU);
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IF !CC JUMP inext;
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/* extract page size (17:16)*/
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R3 = EXTRACT(R2, R1.L) (Z);
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/* add page size to addr to get range */
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P5 = R3;
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P5 = P0 + (P5 << 2); /* scaled, for int access*/
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R3 = [P5];
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R3 = R3 + R4;
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/* See if failed address < (start address + page size) */
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CC = R0 < R3(IU);
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IF !CC JUMP inext;
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/* We've found a CPLB in the config table that covers
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* the faulting address, so install this CPLB into the
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* last entry of the table.
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*/
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P1.L = (ICPLB_DATA15 & 0xFFFF); /*ICPLB_DATA15*/
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P1.H = (ICPLB_DATA15 >> 16);
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[P1] = R2;
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[P1-0x100] = R4;
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#ifdef CONFIG_CPLB_INFO
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R3 = [P3];
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R3 += 1;
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[P3] = R3;
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#endif
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/* P4 points to IMEM_CONTROL, and R5 contains its old
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* value, after we disabled ICPLBS. Re-enable them.
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*/
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BITSET(R5,ENICPLB_P);
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CLI R2;
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SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
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.align 8;
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[P4] = R5;
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SSYNC;
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STI R2;
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( R7:0,P5:0 ) = [SP++];
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R0 = CPLB_RELOADED;
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RTS;
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/* FAILED CASES*/
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no_page_in_table:
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( R7:0,P5:0 ) = [SP++];
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R0 = CPLB_NO_ADDR_MATCH;
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RTS;
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all_locked:
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( R7:0,P5:0 ) = [SP++];
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R0 = CPLB_NO_UNLOCKED;
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RTS;
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prot_violation:
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( R7:0,P5:0 ) = [SP++];
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R0 = CPLB_PROT_VIOL;
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RTS;
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dcplb_write:
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/* if a DCPLB is marked as write-back (CPLB_WT==0), and
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* it is clean (CPLB_DIRTY==0), then a write to the
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* CPLB's page triggers a protection violation. We have to
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* mark the CPLB as dirty, to indicate that there are
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* pending writes associated with the CPLB.
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*/
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P4.L = (DCPLB_STATUS & 0xFFFF);
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P4.H = (DCPLB_STATUS >> 16);
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P3.L = (DCPLB_DATA0 & 0xFFFF);
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P3.H = (DCPLB_DATA0 >> 16);
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R5 = [P4];
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/* A protection violation can be caused by more than just writes
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* to a clean WB page, so we have to ensure that:
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* - It's a write
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* - to a clean WB page
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* - and is allowed in the mode the access occurred.
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*/
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CC = BITTST(R5, 16); /* ensure it was a write*/
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IF !CC JUMP prot_violation;
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/* to check the rest, we have to retrieve the DCPLB.*/
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/* The low half of DCPLB_STATUS is a bit mask*/
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R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/
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R3 = 30; /* so we can use this to determine the offset*/
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R2.L = SIGNBITS R2;
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R2 = R2.L (Z); /* into the DCPLB table.*/
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R3 = R3 - R2;
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P4 = R3;
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P3 = P3 + (P4<<2);
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R3 = [P3]; /* Retrieve the CPLB*/
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/* Now we can check whether it's a clean WB page*/
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CC = BITTST(R3, 14); /* 0==WB, 1==WT*/
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IF CC JUMP prot_violation;
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CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/
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IF CC JUMP prot_violation;
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/* Check whether the write is allowed in the mode that was active.*/
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R2 = 1<<3; /* checking write in user mode*/
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CC = BITTST(R5, 17); /* 0==was user, 1==was super*/
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R5 = CC;
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R2 <<= R5; /* if was super, check write in super mode*/
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R2 = R3 & R2;
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CC = R2 == 0;
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IF CC JUMP prot_violation;
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/* It's a genuine write-to-clean-page.*/
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BITSET(R3, 7); /* mark as dirty*/
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[P3] = R3; /* and write back.*/
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CSYNC;
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( R7:0,P5:0 ) = [SP++];
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R0 = CPLB_RELOADED;
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RTS;
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dcplb_miss_compare:
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/* Data CPLB Miss event. We need to choose a CPLB to
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* evict, and then locate a new CPLB to install from the
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* config table, that covers the faulting address.
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*/
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P1.L = (DCPLB_DATA15 & 0xFFFF);
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P1.H = (DCPLB_DATA15 >> 16);
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P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
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P4.H = (DCPLB_FAULT_ADDR >> 16);
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R4 = [P4];
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I0 = R4;
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/* The replacement procedure for DCPLBs*/
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R6 = R1; /* Save for later*/
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/* Turn off CPLBs while we work.*/
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P4.L = (DMEM_CONTROL & 0xFFFF);
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P4.H = (DMEM_CONTROL >> 16);
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R5 = [P4];
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BITCLR(R5,ENDCPLB_P);
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CLI R0;
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SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
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.align 8;
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[P4] = R5;
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SSYNC;
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STI R0;
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/* Start looking for a CPLB to evict. Our order of preference
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* is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
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* are no good.
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*/
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I1.L = (DCPLB_DATA0 & 0xFFFF);
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I1.H = (DCPLB_DATA0 >> 16);
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P1 = 3;
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P2 = 16;
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I2.L = dcplb_preference;
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I2.H = dcplb_preference;
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LSETUP(sdsearch1, edsearch1) LC0 = P1;
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sdsearch1:
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R0 = [I2++]; /* Get the bits we're interested in*/
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P0 = I1; /* Go back to start of table*/
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LSETUP (sdsearch2, edsearch2) LC1 = P2;
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sdsearch2:
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R1 = [P0++]; /* Fetch each installed CPLB in turn*/
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R2 = R1 & R0; /* and test for interesting bits.*/
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CC = R2 == 0; /* If none are set, it'll do.*/
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IF !CC JUMP skip_stack_check;
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R2 = [P0 - 0x104]; /* R2 - PageStart */
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P3.L = page_size_table; /* retrive end address */
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P3.H = page_size_table; /* retrive end address */
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R3 = 0x2; /* 0th - position, 2 bits -length */
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nop; /*Anamoly 05000209*/
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R7 = EXTRACT(R1,R3.l);
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R7 = R7 << 2; /* Page size index offset */
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P5 = R7;
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P3 = P3 + P5;
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R7 = [P3]; /* page size in 1K bytes */
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R7 = R7 << 0xA; /* in bytes * 1024*/
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R7 = R2 + R7; /* R7 - PageEnd */
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R4 = SP; /* Test SP is in range */
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CC = R7 < R4; /* if PageEnd < SP */
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IF CC JUMP dfound_victim;
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R3 = 0x284; /* stack length from start of trap till the point */
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/* 20 stack locations for future modifications */
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R4 = R4 + R3;
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CC = R4 < R2; /* if SP + stacklen < PageStart */
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IF CC JUMP dfound_victim;
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skip_stack_check:
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edsearch2: NOP;
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edsearch1: NOP;
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/* If we got here, we didn't find a DCPLB we considered
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* replacable, which means all of them were locked.
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*/
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JUMP all_locked;
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dfound_victim:
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#ifdef CONFIG_CPLB_INFO
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R1 = [P0 - 0x104];
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P2.L = dpdt_table;
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P2.H = dpdt_table;
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P3.L = dpdt_swapcount_table;
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P3.H = dpdt_swapcount_table;
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P3 += -4;
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dicount:
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R2 = [P2];
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P2 += 8;
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P3 += 8;
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CC = R2==-1;
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IF CC JUMP dicount_done;
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CC = R1==R2;
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IF !CC JUMP dicount;
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R1 = [P3];
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R1 += 1;
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[P3] = R1;
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CSYNC;
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dicount_done:
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#endif
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/* Clean down the hardware loops*/
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R2 = 0;
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LC1 = R2;
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LC0 = R2;
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/* There's a suitable victim in [P0-4] (because we've
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* advanced already). If it's a valid dirty write-back
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* CPLB, we need to flush the pending writes first.
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*/
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CC = BITTST(R1, 0); /* Is it valid?*/
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IF !CC JUMP Ddoverwrite;/* nope.*/
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CC = BITTST(R1, 7); /* Is it dirty?*/
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IF !CC JUMP Ddoverwrite (BP); /* Nope.*/
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CC = BITTST(R1, 14); /* Is it Write-Through?*/
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IF CC JUMP Ddoverwrite; /* Yep*/
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/* This is a dirty page, so we need to flush all writes
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* that are pending on the page.
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*/
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/* Retrieve the page start address*/
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R0 = [P0 - 0x104];
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[--sp] = rets;
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CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/
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rets = [sp++];
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Ddoverwrite:
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/* [P0-4] is a suitable victim CPLB, so we want to
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* overwrite it by moving all the following CPLBs
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* one space closer to the start.
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*/
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R1.L = ((DCPLB_DATA15+4) & 0xFFFF); /*DCPLB_DATA15+4*/
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R1.H = ((DCPLB_DATA15+4) >> 16);
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R0 = P0;
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/* If the victim happens to be in DCPLB15,
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* we don't need to move anything.
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*/
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CC = R1 == R0;
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IF CC JUMP de_moved;
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R1 = R1 - R0;
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R1 >>= 2;
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P1 = R1;
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LSETUP(ds_move, de_move) LC0=P1;
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ds_move:
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R0 = [P0++]; /* move data */
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[P0 - 8] = R0;
|
|
R0 = [P0-0x104] /* move address */
|
|
de_move: [P0-0x108] = R0;
|
|
|
|
/* We've now made space in DCPLB15 for the new CPLB to be
|
|
* installed. The next stage is to locate a CPLB in the
|
|
* config table that covers the faulting address.
|
|
*/
|
|
|
|
de_moved:NOP;
|
|
R0 = I0; /* Our faulting address */
|
|
|
|
P2.L = dpdt_table;
|
|
P2.H = dpdt_table;
|
|
#ifdef CONFIG_CPLB_INFO
|
|
P3.L = dpdt_swapcount_table;
|
|
P3.H = dpdt_swapcount_table;
|
|
P3 += -8;
|
|
#endif
|
|
|
|
P1.L = page_size_table;
|
|
P1.H = page_size_table;
|
|
|
|
/* An extraction pattern, to retrieve bits 17:16.*/
|
|
|
|
R1 = (16<<8)|2;
|
|
dnext: R4 = [P2++]; /* address */
|
|
R2 = [P2++]; /* data */
|
|
#ifdef CONFIG_CPLB_INFO
|
|
P3 += 8;
|
|
#endif
|
|
|
|
CC = R4 == -1;
|
|
IF CC JUMP no_page_in_table;
|
|
|
|
/* See if failed address > start address */
|
|
CC = R4 <= R0(IU);
|
|
IF !CC JUMP dnext;
|
|
|
|
/* extract page size (17:16)*/
|
|
R3 = EXTRACT(R2, R1.L) (Z);
|
|
|
|
/* add page size to addr to get range */
|
|
|
|
P5 = R3;
|
|
P5 = P1 + (P5 << 2);
|
|
R3 = [P5];
|
|
R3 = R3 + R4;
|
|
|
|
/* See if failed address < (start address + page size) */
|
|
CC = R0 < R3(IU);
|
|
IF !CC JUMP dnext;
|
|
|
|
/* We've found the CPLB that should be installed, so
|
|
* write it into CPLB15, masking off any caching bits
|
|
* if necessary.
|
|
*/
|
|
|
|
P1.L = (DCPLB_DATA15 & 0xFFFF);
|
|
P1.H = (DCPLB_DATA15 >> 16);
|
|
|
|
/* If the DCPLB has cache bits set, but caching hasn't
|
|
* been enabled, then we want to mask off the cache-in-L1
|
|
* bit before installing. Moreover, if caching is off, we
|
|
* also want to ensure that the DCPLB has WT mode set, rather
|
|
* than WB, since WB pages still trigger first-write exceptions
|
|
* even when not caching is off, and the page isn't marked as
|
|
* cachable. Finally, we could mark the page as clean, not dirty,
|
|
* but we choose to leave that decision to the user; if the user
|
|
* chooses to have a CPLB pre-defined as dirty, then they always
|
|
* pay the cost of flushing during eviction, but don't pay the
|
|
* cost of first-write exceptions to mark the page as dirty.
|
|
*/
|
|
|
|
#ifdef CONFIG_BLKFIN_WT
|
|
BITSET(R6, 14); /* Set WT*/
|
|
#endif
|
|
|
|
[P1] = R2;
|
|
[P1-0x100] = R4;
|
|
#ifdef CONFIG_CPLB_INFO
|
|
R3 = [P3];
|
|
R3 += 1;
|
|
[P3] = R3;
|
|
#endif
|
|
|
|
/* We've installed the CPLB, so re-enable CPLBs. P4
|
|
* points to DMEM_CONTROL, and R5 is the value we
|
|
* last wrote to it, when we were disabling CPLBs.
|
|
*/
|
|
|
|
BITSET(R5,ENDCPLB_P);
|
|
CLI R2;
|
|
.align 8;
|
|
[P4] = R5;
|
|
SSYNC;
|
|
STI R2;
|
|
|
|
( R7:0,P5:0 ) = [SP++];
|
|
R0 = CPLB_RELOADED;
|
|
RTS;
|
|
|
|
.data
|
|
.align 4;
|
|
page_size_table:
|
|
.byte4 0x00000400; /* 1K */
|
|
.byte4 0x00001000; /* 4K */
|
|
.byte4 0x00100000; /* 1M */
|
|
.byte4 0x00400000; /* 4M */
|
|
|
|
.align 4;
|
|
dcplb_preference:
|
|
.byte4 0x00000001; /* valid bit */
|
|
.byte4 0x00000082; /* dirty+lock bits */
|
|
.byte4 0x00000002; /* lock bit */
|