u-boot/board/jse
Josh Boyer 317734966e Dual-license IBM code contributions
It was brought to our attention that U-Boot contains code derived from the
IBM OpenBIOS source code originally provided with some of the older PowerPC
4xx development boards.  As a result, the original license of this code has
been carried in the various files for a number of years in the U-Boot project.

IBM is dual-licensing the IBM code contributions already present in U-Boot
under either the terms of the GNU General Public License version 2, or the
original code license already present.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2009-08-09 23:15:33 +02:00
..
config.mk * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
flash.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
host_bridge.c * Code cleanup, mostly for GCC-3.3.x 2004-12-31 09:32:47 +00:00
init.S Dual-license IBM code contributions 2009-08-09 23:15:33 +02:00
jse.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
jse_priv.h * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
Makefile Cleanup out-or-tree building for some boards (.depend) 2008-07-02 23:49:18 +02:00
README.txt * Patch by Stephen Williams, 01 Apr 2004: 2004-04-15 23:14:49 +00:00
sdram.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
u-boot.lds Fix all linker script to handle all rodata sections 2009-03-20 22:39:12 +01:00

JSE Configuration Details

Memory Bank 0 -- Flash chip
---------------------------

0xfff00000 - 0xffffffff

The flash chip is really only 512Kbytes, but the high address bit of
the 1Meg region is ignored, so the flash is replicated through the
region. Thus, this is consistent with a flash base address 0xfff80000.

The placement at the end is to be consistent with reset behavior,
where the processor itself initially uses this bus to load the branch
vector and start running.

On-Chip Memory
--------------

0xf4000000 - 0xf4000fff

The 405GPr includes a 4K on-chip memory that can be placed however
software chooses. I choose to place the memory at this address, to
keep it out of the cachable areas.


Memory Bank 1 -- SystemACE Controller
-------------------------------------

0xf0000000 - 0xf00fffff

The SystemACE chip is along on peripheral bank CS#1. We don't need
much space, but 1Meg is the smallest we can configure the chip to
allocate. We need it far away from the flash region, because this
region is set to be non-cached.


Internal Peripherals
--------------------

0xef600300 - 0xef6008ff

These are scattered various peripherals internal to the PPC405GPr
chip.

SDRAM
-----

0x00000000 - 0x07ffffff  (128 MBytes)