Xingyu Wu 6c4b50e6de riscv: dts: jh7110: Add clock source from PLL ... Change the PLL clock source from syscrg to sys_syscon child node. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2023-07-24 13:21:06 +08:00
..
cpu	riscv: setup per-hart stack earlier	2023-07-24 13:17:26 +08:00
dts	riscv: dts: jh7110: Add clock source from PLL	2023-07-24 13:21:06 +08:00
include/asm	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
lib	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
config.mk	riscv: Support CONFIG_REMAKE_ELF	2023-04-20 20:45:08 +08:00
Kconfig	riscv: t-head: licheepi4a: initial support added	2023-07-12 13:21:41 +08:00
Makefile	riscv: support building double-float modules	2022-10-20 15:22:21 +08:00