Murali Karicheri 6c343825dd ARM: keystone: ddr3: workaround for ddr3a/3b memory issue ... This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>		2014-09-17 21:06:56 -04:00
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asm	ARM: keystone: ddr3: workaround for ddr3a/3b memory issue	2014-09-17 21:06:56 -04:00