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c05ed00afb
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
392 lines
11 KiB
C
392 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Atmel Corporation
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* Bo Shen <voice.shen@atmel.com>
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*
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* Copyright (C) 2015 Atmel Corporation
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* Wenyou Yang <wenyou.yang@atmel.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/at91_common.h>
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#include <linux/delay.h>
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#define SAMA5D3_MPDDRC_VERSION 0x140
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static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
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int mode,
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u32 ram_address)
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{
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writel(mode, &mpddr->mr);
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dmb();
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writel(0, ram_address);
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}
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static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr)
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{
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struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
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u16 version = readl(&mpddr->version) & 0xffff;
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if ((version >= SAMA5D3_MPDDRC_VERSION) &&
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(cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
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return 0;
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return 1;
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}
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int ddr2_init(const unsigned int base,
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const unsigned int ram_address,
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const struct atmel_mpddrc_config *mpddr_value)
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{
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const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
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u32 ba_off, cr;
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/* Compute bank offset according to NC in configuration register */
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ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
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if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
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ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
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ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
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/* Program the memory device type into the memory device register */
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writel(mpddr_value->md, &mpddr->md);
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/* Program the configuration register */
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writel(mpddr_value->cr, &mpddr->cr);
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/* Program the timing register */
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writel(mpddr_value->tpr0, &mpddr->tpr0);
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writel(mpddr_value->tpr1, &mpddr->tpr1);
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writel(mpddr_value->tpr2, &mpddr->tpr2);
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/* Issue a NOP command */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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/* A 200 us is provided to precede any signal toggle */
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udelay(200);
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/* Issue a NOP command */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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/* Issue an all banks precharge command */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
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/* Issue an extended mode register set(EMRS2) to choose operation */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x2 << ba_off));
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/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x3 << ba_off));
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/*
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* Issue an extended mode register set(EMRS1) to enable DLL and
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* program D.I.C (output driver impedance control)
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x1 << ba_off));
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/* Enable DLL reset */
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cr = readl(&mpddr->cr);
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writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
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/* A mode register set(MRS) cycle is issued to reset DLL */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
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/* Issue an all banks precharge command */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
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/* Two auto-refresh (CBR) cycles are provided */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
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/* Disable DLL reset */
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cr = readl(&mpddr->cr);
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writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
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/* A mode register set (MRS) cycle is issued to disable DLL reset */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
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/* Set OCD calibration in default state */
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cr = readl(&mpddr->cr);
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writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
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/*
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* An extended mode register set (EMRS1) cycle is issued
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* to OCD default value
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x1 << ba_off));
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/* OCD calibration mode exit */
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cr = readl(&mpddr->cr);
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writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
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/*
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* An extended mode register set (EMRS1) cycle is issued
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* to enable OCD exit
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x1 << ba_off));
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/* A nornal mode command is provided */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
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/* Perform a write access to any DDR2-SDRAM address */
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writel(0, ram_address);
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/* Write the refresh rate */
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writel(mpddr_value->rtr, &mpddr->rtr);
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return 0;
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}
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int ddr3_init(const unsigned int base,
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const unsigned int ram_address,
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const struct atmel_mpddrc_config *mpddr_value)
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{
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struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
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u32 ba_off;
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/* Compute bank offset according to NC in configuration register */
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ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
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if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
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ba_off += ((mpddr_value->cr &
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ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
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ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
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/* Program the memory device type */
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writel(mpddr_value->md, &mpddr->md);
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/*
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* Program features of the DDR3-SDRAM device and timing parameters
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*/
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writel(mpddr_value->cr, &mpddr->cr);
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writel(mpddr_value->tpr0, &mpddr->tpr0);
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writel(mpddr_value->tpr1, &mpddr->tpr1);
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writel(mpddr_value->tpr2, &mpddr->tpr2);
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/* A NOP command is issued to the DDR3-SRAM */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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/* A pause of at least 500us must be observed before a single toggle. */
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udelay(500);
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/* A NOP command is issued to the DDR3-SDRAM */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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/*
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* An Extended Mode Register Set (EMRS2) cycle is issued to choose
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* between commercial or high temperature operations.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x2 << ba_off));
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/*
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* Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
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* the Extended Mode Register to 0.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x3 << ba_off));
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/*
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* An Extended Mode Register Set (EMRS1) cycle is issued to disable and
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* to program O.D.S. (Output Driver Strength).
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
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ram_address + (0x1 << ba_off));
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/*
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* Write a one to the DLL bit (enable DLL reset) in the MPDDRC
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* Configuration Register.
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*/
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/* A Mode Register Set (MRS) cycle is issued to reset DLL. */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
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udelay(50);
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/*
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* A Calibration command (MRS) is issued to calibrate RTT and RON
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* values for the Process Voltage Temperature (PVT).
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_DEEP_CMD, ram_address);
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/* A Normal Mode command is provided. */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
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/* Perform a write access to any DDR3-SDRAM address. */
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writel(0, ram_address);
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/*
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* Write the refresh rate into the COUNT field in the MPDDRC
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* Refresh Timer Register (MPDDRC_RTR):
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*/
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writel(mpddr_value->rtr, &mpddr->rtr);
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return 0;
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}
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int lpddr2_init(const unsigned int base,
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const unsigned int ram_address,
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const struct atmel_mpddrc_config *mpddr_value)
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{
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struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
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u32 reg;
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writel(mpddr_value->lpddr23_lpr, &mpddr->lpddr23_lpr);
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writel(mpddr_value->tim_cal, &mpddr->tim_cal);
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/* 1. Program the memory device type */
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writel(mpddr_value->md, &mpddr->md);
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/*
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* 2. Program features of the LPDDR2-SDRAM device and timing parameters
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*/
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writel(mpddr_value->cr, &mpddr->cr);
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writel(mpddr_value->tpr0, &mpddr->tpr0);
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writel(mpddr_value->tpr1, &mpddr->tpr1);
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writel(mpddr_value->tpr2, &mpddr->tpr2);
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/* 3. A NOP command is issued to the LPDDR2-SDRAM */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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/*
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* 3bis. Add memory barrier then Perform a write access to
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* any low-power DDR2-SDRAM address to acknowledge the command.
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*/
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dmb();
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writel(0, ram_address);
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/* 4. A pause of at least 100 ns must be observed before a single toggle */
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udelay(1);
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/* 5. A NOP command is issued to the LPDDR2-SDRAM */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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/* 6. A pause of at least 200 us must be observed before a Reset Command */
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udelay(200);
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/* 7. A Reset command is issued to the low-power DDR2-SDRAM. */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(63), ram_address);
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/*
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* 8. A pause of at least tINIT5 must be observed before issuing
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* any commands
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*/
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udelay(1);
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/* 9. A Calibration command is issued to the low-power DDR2-SDRAM. */
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reg = readl(&mpddr->cr);
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reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET;
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reg |= ATMEL_MPDDRC_CR_ZQ_RESET;
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writel(reg, &mpddr->cr);
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(10), ram_address);
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/*
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* 9bis: The ZQ Calibration command is now issued.
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* Program the type of calibration in the MPDDRC_CR: set the
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* ZQ field to the SHORT value.
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*/
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reg = readl(&mpddr->cr);
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reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET;
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reg |= ATMEL_MPDDRC_CR_ZQ_SHORT;
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writel(reg, &mpddr->cr);
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/*
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* 10: A Mode Register Write command with 1 to the MRS field
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* is issued to the low-power DDR2-SDRAM.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(1), ram_address);
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/*
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* 11: A Mode Register Write command with 2 to the MRS field
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* is issued to the low-power DDR2-SDRAM.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(2), ram_address);
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/*
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* 12: A Mode Register Write command with 3 to the MRS field
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* is issued to the low-power DDR2-SDRAM.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(3), ram_address);
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/*
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* 13: A Mode Register Write command with 16 to the MRS field
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* is issued to the low-power DDR2-SDRAM.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(16), ram_address);
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/*
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* 14: In the DDR Configuration Register, open the input buffers.
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*/
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#ifdef CONFIG_ATMEL_SFR
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configure_ddrcfg_input_buffers(true);
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#endif
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/* 15. A NOP command is issued to the LPDDR2-SDRAM */
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
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/*
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* 16: A Mode Register Write command with 5 to the MRS field
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* is issued to the low-power DDR2-SDRAM.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(5), ram_address);
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/*
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* 17: A Mode Register Write command with 6 to the MRS field
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* is issued to the low-power DDR2-SDRAM.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(6), ram_address);
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/*
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* 18: A Mode Register Write command with 8 to the MRS field
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* is issued to the low-power DDR2-SDRAM.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(8), ram_address);
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/*
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* 19: A Mode Register Write command with 0 to the MRS field
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* is issued to the low-power DDR2-SDRAM.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
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ATMEL_MPDDRC_MR_MRS(0), ram_address);
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/*
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* 20: A Normal Mode command is provided.
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*/
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atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
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/* 21: In the DDR Configuration Register, close the input buffers. */
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#ifdef CONFIG_ATMEL_SFR
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configure_ddrcfg_input_buffers(false);
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#endif
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/*
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* 22: Write the refresh rate into the COUNT field in the MPDDRC
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* Refresh Timer Register.
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*/
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writel(mpddr_value->rtr, &mpddr->rtr);
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/* 23. Configre CAL MR4 register */
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writel(mpddr_value->cal_mr4, &mpddr->cal_mr4);
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return 0;
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}
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