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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
288 lines
6.8 KiB
C
288 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
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*
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* Copyright (C) 2005 David Brownell
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/clk.h>
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#if !defined(CONFIG_AT91FAMILY)
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# error You need to define CONFIG_AT91FAMILY in your board config!
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#endif
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#define EN_PLLB_TIMEOUT 500
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DECLARE_GLOBAL_DATA_PTR;
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static unsigned long at91_css_to_rate(unsigned long css)
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{
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switch (css) {
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case AT91_PMC_MCKR_CSS_SLOW:
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return CFG_SYS_AT91_SLOW_CLOCK;
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case AT91_PMC_MCKR_CSS_MAIN:
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return gd->arch.main_clk_rate_hz;
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case AT91_PMC_MCKR_CSS_PLLA:
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return gd->arch.plla_rate_hz;
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case AT91_PMC_MCKR_CSS_PLLB:
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return gd->arch.pllb_rate_hz;
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}
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return 0;
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}
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#ifdef CONFIG_USB_ATMEL
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static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
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{
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unsigned i, div = 0, mul = 0, diff = 1 << 30;
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unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
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/* PLL output max 240 MHz (or 180 MHz per errata) */
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if (out_freq > 240000000)
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goto fail;
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for (i = 1; i < 256; i++) {
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int diff1;
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unsigned input, mul1;
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/*
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* PLL input between 1MHz and 32MHz per spec, but lower
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* frequences seem necessary in some cases so allow 100K.
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* Warning: some newer products need 2MHz min.
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*/
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input = main_freq / i;
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#if defined(CONFIG_AT91SAM9G20)
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if (input < 2000000)
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continue;
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#endif
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if (input < 100000)
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continue;
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if (input > 32000000)
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continue;
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mul1 = out_freq / input;
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#if defined(CONFIG_AT91SAM9G20)
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if (mul > 63)
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continue;
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#endif
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if (mul1 > 2048)
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continue;
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if (mul1 < 2)
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goto fail;
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diff1 = out_freq - input * mul1;
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if (diff1 < 0)
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diff1 = -diff1;
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if (diff > diff1) {
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diff = diff1;
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div = i;
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mul = mul1;
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if (diff == 0)
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break;
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}
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}
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if (i == 256 && diff > (out_freq >> 5))
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goto fail;
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return ret | ((mul - 1) << 16) | div;
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fail:
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return 0;
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}
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#endif
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static u32 at91_pll_rate(u32 freq, u32 reg)
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{
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unsigned mul, div;
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div = reg & 0xff;
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mul = (reg >> 16) & 0x7ff;
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if (div && mul) {
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freq /= div;
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freq *= mul + 1;
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} else
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freq = 0;
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return freq;
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}
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int at91_clock_init(unsigned long main_clock)
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{
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unsigned freq, mckr;
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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#ifndef CFG_SYS_AT91_MAIN_CLOCK
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unsigned tmp;
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/*
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* When the bootloader initialized the main oscillator correctly,
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* there's no problem using the cycle counter. But if it didn't,
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* or when using oscillator bypass mode, we must be told the speed
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* of the main clock.
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*/
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if (!main_clock) {
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do {
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tmp = readl(&pmc->mcfr);
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} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
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tmp &= AT91_PMC_MCFR_MAINF_MASK;
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main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
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}
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#endif
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gd->arch.main_clk_rate_hz = main_clock;
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/* report if PLLA is more than mildly overclocked */
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gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
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#ifdef CONFIG_USB_ATMEL
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/*
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* USB clock init: choose 48 MHz PLLB value,
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* disable 48MHz clock during usb peripheral suspend.
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*
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* REVISIT: assumes MCK doesn't derive from PLLB!
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*/
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gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
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AT91_PMC_PLLBR_USBDIV_2;
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gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
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gd->arch.at91_pllb_usb_init);
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#endif
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/*
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* MCK and CPU derive from one of those primary clocks.
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* For now, assume this parentage won't change.
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*/
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mckr = readl(&pmc->mckr);
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
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|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
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/* plla divisor by 2 */
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gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
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#endif
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gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
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freq = gd->arch.mck_rate_hz;
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#if defined(CONFIG_AT91SAM9X5)
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/* different in prescale on at91sam9x5 */
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freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4));
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#else
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freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
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#endif
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#if defined(CONFIG_AT91SAM9G20)
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/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
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gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
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freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
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if (mckr & AT91_PMC_MCKR_MDIV_MASK)
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freq /= 2; /* processor clock division */
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#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
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|| defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
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/* mdiv <==> divisor
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* 0 <==> 1
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* 1 <==> 2
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* 2 <==> 4
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* 3 <==> 3
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*/
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gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
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(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
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? freq / 3
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: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
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#else
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gd->arch.mck_rate_hz = freq /
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(1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
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#endif
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gd->arch.cpu_clk_rate_hz = freq;
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return 0;
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}
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#if !defined(AT91_PLL_LOCK_TIMEOUT)
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#define AT91_PLL_LOCK_TIMEOUT 1000000
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#endif
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void at91_plla_init(u32 pllar)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(pllar, &pmc->pllar);
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while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))
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;
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}
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void at91_pllb_init(u32 pllbr)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(pllbr, &pmc->pllbr);
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while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))
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;
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}
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void at91_mck_init(u32 mckr)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 tmp;
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tmp = readl(&pmc->mckr);
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tmp &= ~AT91_PMC_MCKR_PRES_MASK;
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tmp |= mckr & AT91_PMC_MCKR_PRES_MASK;
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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tmp = readl(&pmc->mckr);
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tmp &= ~AT91_PMC_MCKR_MDIV_MASK;
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tmp |= mckr & AT91_PMC_MCKR_MDIV_MASK;
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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tmp = readl(&pmc->mckr);
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tmp &= ~AT91_PMC_MCKR_PLLADIV_MASK;
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tmp |= mckr & AT91_PMC_MCKR_PLLADIV_MASK;
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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tmp = readl(&pmc->mckr);
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tmp &= ~AT91_PMC_MCKR_CSS_MASK;
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tmp |= mckr & AT91_PMC_MCKR_CSS_MASK;
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writel(tmp, &pmc->mckr);
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while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
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;
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}
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int at91_pllb_clk_enable(u32 pllbr)
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{
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struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
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ulong start_time, tmp_time;
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start_time = get_timer(0);
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writel(pllbr, &pmc->pllbr);
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while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
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tmp_time = get_timer(0);
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if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
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printf("ERROR: failed to enable PLLB\n");
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return -1;
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}
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}
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return 0;
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}
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int at91_pllb_clk_disable(void)
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{
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struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
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ulong start_time, tmp_time;
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start_time = get_timer(0);
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writel(0, &pmc->pllbr);
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while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
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tmp_time = get_timer(0);
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if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
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printf("ERROR: failed to disable PLLB\n");
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return -1;
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}
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}
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return 0;
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}
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