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e3e01a6f94
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC carrier board. This patch is based on the corresponding Linux v6.5 device tree (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
1273 lines
38 KiB
Text
1273 lines
38 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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/ {
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compatible = "renesas,r9a07g044";
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#address-cells = <2>;
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#size-cells = <2>;
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audio_clk1: audio1-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by boards that provide it */
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clock-frequency = <0>;
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};
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audio_clk2: audio2-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by boards that provide it */
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clock-frequency = <0>;
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};
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
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extal_clk: extal-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-150000000 {
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opp-hz = /bits/ 64 <150000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <300000>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <300000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <300000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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reg = <0>;
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device_type = "cpu";
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#cooling-cells = <2>;
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next-level-cache = <&L3_CA55>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu1: cpu@100 {
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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device_type = "cpu";
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next-level-cache = <&L3_CA55>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
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operating-points-v2 = <&cluster0_opp>;
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};
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L3_CA55: cache-controller-0 {
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compatible = "cache";
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cache-unified;
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cache-size = <0x40000>;
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cache-level = <3>;
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};
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};
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gpu_opp_table: opp-table-1 {
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compatible = "operating-points-v2";
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <1100000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <1100000>;
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};
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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opp-microvolt = <1100000>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <1100000>;
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};
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opp-125000000 {
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opp-hz = /bits/ 64 <125000000>;
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opp-microvolt = <1100000>;
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};
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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opp-microvolt = <1100000>;
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};
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opp-62500000 {
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opp-hz = /bits/ 64 <62500000>;
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opp-microvolt = <1100000>;
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};
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opp-50000000 {
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opp-hz = /bits/ 64 <50000000>;
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opp-microvolt = <1100000>;
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};
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};
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pmu {
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compatible = "arm,cortex-a55-pmu";
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interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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mtu3: timer@10001200 {
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compatible = "renesas,r9a07g044-mtu3",
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"renesas,rz-mtu3";
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reg = <0 0x10001200 0 0xb00>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
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"tgiv0", "tgie0", "tgif0",
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"tgia1", "tgib1", "tgiv1", "tgiu1",
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"tgia2", "tgib2", "tgiv2", "tgiu2",
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"tgia3", "tgib3", "tgic3", "tgid3",
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"tgiv3",
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"tgia4", "tgib4", "tgic4", "tgid4",
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"tgiv4",
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"tgiu5", "tgiv5", "tgiw5",
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"tgia6", "tgib6", "tgic6", "tgid6",
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"tgiv6",
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"tgia7", "tgib7", "tgic7", "tgid7",
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"tgiv7",
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"tgia8", "tgib8", "tgic8", "tgid8",
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"tgiv8", "tgiu8";
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clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
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#pwm-cells = <2>;
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status = "disabled";
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};
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ssi0: ssi@10049c00 {
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compatible = "renesas,r9a07g044-ssi",
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"renesas,rz-ssi";
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reg = <0 0x10049c00 0 0x400>;
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interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "int_req", "dma_rx", "dma_tx";
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clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
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<&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
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<&audio_clk1>, <&audio_clk2>;
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clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
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resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
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dmas = <&dmac 0x2655>, <&dmac 0x2656>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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ssi1: ssi@1004a000 {
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compatible = "renesas,r9a07g044-ssi",
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"renesas,rz-ssi";
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reg = <0 0x1004a000 0 0x400>;
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interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "int_req", "dma_rx", "dma_tx";
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clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
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<&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
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<&audio_clk1>, <&audio_clk2>;
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clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
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resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
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dmas = <&dmac 0x2659>, <&dmac 0x265a>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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ssi2: ssi@1004a400 {
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compatible = "renesas,r9a07g044-ssi",
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"renesas,rz-ssi";
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reg = <0 0x1004a400 0 0x400>;
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interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "int_req", "dma_rt";
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clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
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<&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
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<&audio_clk1>, <&audio_clk2>;
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clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
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resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
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dmas = <&dmac 0x265f>;
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dma-names = "rt";
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power-domains = <&cpg>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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ssi3: ssi@1004a800 {
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compatible = "renesas,r9a07g044-ssi",
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"renesas,rz-ssi";
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reg = <0 0x1004a800 0 0x400>;
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interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "int_req", "dma_rx", "dma_tx";
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clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
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<&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
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<&audio_clk1>, <&audio_clk2>;
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clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
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resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
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dmas = <&dmac 0x2661>, <&dmac 0x2662>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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spi0: spi@1004ac00 {
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compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
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reg = <0 0x1004ac00 0 0x400>;
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interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
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resets = <&cpg R9A07G044_RSPI0_RST>;
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dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@1004b000 {
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compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
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reg = <0 0x1004b000 0 0x400>;
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interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
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resets = <&cpg R9A07G044_RSPI1_RST>;
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dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@1004b400 {
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compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
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reg = <0 0x1004b400 0 0x400>;
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interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
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resets = <&cpg R9A07G044_RSPI2_RST>;
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dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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scif0: serial@1004b800 {
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compatible = "renesas,scif-r9a07g044";
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reg = <0 0x1004b800 0 0x400>;
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interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
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status = "disabled";
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};
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scif1: serial@1004bc00 {
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compatible = "renesas,scif-r9a07g044";
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reg = <0 0x1004bc00 0 0x400>;
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interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
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status = "disabled";
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};
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scif2: serial@1004c000 {
|
|
compatible = "renesas,scif-r9a07g044";
|
|
reg = <0 0x1004c000 0 0x400>;
|
|
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "eri", "rxi", "txi",
|
|
"bri", "dri", "tei";
|
|
clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
|
|
clock-names = "fck";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@1004c400 {
|
|
compatible = "renesas,scif-r9a07g044";
|
|
reg = <0 0x1004c400 0 0x400>;
|
|
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "eri", "rxi", "txi",
|
|
"bri", "dri", "tei";
|
|
clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
|
|
clock-names = "fck";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@1004c800 {
|
|
compatible = "renesas,scif-r9a07g044";
|
|
reg = <0 0x1004c800 0 0x400>;
|
|
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "eri", "rxi", "txi",
|
|
"bri", "dri", "tei";
|
|
clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
|
|
clock-names = "fck";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sci0: serial@1004d000 {
|
|
compatible = "renesas,r9a07g044-sci", "renesas,sci";
|
|
reg = <0 0x1004d000 0 0x400>;
|
|
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "eri", "rxi", "txi", "tei";
|
|
clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
|
|
clock-names = "fck";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_SCI0_RST>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sci1: serial@1004d400 {
|
|
compatible = "renesas,r9a07g044-sci", "renesas,sci";
|
|
reg = <0 0x1004d400 0 0x400>;
|
|
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "eri", "rxi", "txi", "tei";
|
|
clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
|
|
clock-names = "fck";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_SCI1_RST>;
|
|
status = "disabled";
|
|
};
|
|
|
|
canfd: can@10050000 {
|
|
compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
|
|
reg = <0 0x10050000 0 0x8000>;
|
|
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "g_err", "g_recc",
|
|
"ch0_err", "ch0_rec", "ch0_trx",
|
|
"ch1_err", "ch1_rec", "ch1_trx";
|
|
clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
|
|
<&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
|
|
<&can_clk>;
|
|
clock-names = "fck", "canfd", "can_clk";
|
|
assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
|
|
assigned-clock-rates = <50000000>;
|
|
resets = <&cpg R9A07G044_CANFD_RSTP_N>,
|
|
<&cpg R9A07G044_CANFD_RSTC_N>;
|
|
reset-names = "rstp_n", "rstc_n";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
|
|
channel0 {
|
|
status = "disabled";
|
|
};
|
|
channel1 {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
i2c0: i2c@10058000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
|
|
reg = <0 0x10058000 0 0x400>;
|
|
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
|
"naki", "ali", "tmoi";
|
|
clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
|
|
clock-frequency = <100000>;
|
|
resets = <&cpg R9A07G044_I2C0_MRST>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@10058400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
|
|
reg = <0 0x10058400 0 0x400>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
|
"naki", "ali", "tmoi";
|
|
clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
|
|
clock-frequency = <100000>;
|
|
resets = <&cpg R9A07G044_I2C1_MRST>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@10058800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
|
|
reg = <0 0x10058800 0 0x400>;
|
|
interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
|
"naki", "ali", "tmoi";
|
|
clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
|
|
clock-frequency = <100000>;
|
|
resets = <&cpg R9A07G044_I2C2_MRST>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@10058c00 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
|
|
reg = <0 0x10058c00 0 0x400>;
|
|
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tei", "ri", "ti", "spi", "sti",
|
|
"naki", "ali", "tmoi";
|
|
clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
|
|
clock-frequency = <100000>;
|
|
resets = <&cpg R9A07G044_I2C3_MRST>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc: adc@10059000 {
|
|
compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
|
|
reg = <0 0x10059000 0 0x400>;
|
|
interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
|
|
<&cpg CPG_MOD R9A07G044_ADC_PCLK>;
|
|
clock-names = "adclk", "pclk";
|
|
resets = <&cpg R9A07G044_ADC_PRESETN>,
|
|
<&cpg R9A07G044_ADC_ADRST_N>;
|
|
reset-names = "presetn", "adrst-n";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
channel@0 {
|
|
reg = <0>;
|
|
};
|
|
channel@1 {
|
|
reg = <1>;
|
|
};
|
|
channel@2 {
|
|
reg = <2>;
|
|
};
|
|
channel@3 {
|
|
reg = <3>;
|
|
};
|
|
channel@4 {
|
|
reg = <4>;
|
|
};
|
|
channel@5 {
|
|
reg = <5>;
|
|
};
|
|
channel@6 {
|
|
reg = <6>;
|
|
};
|
|
channel@7 {
|
|
reg = <7>;
|
|
};
|
|
};
|
|
|
|
tsu: thermal@10059400 {
|
|
compatible = "renesas,r9a07g044-tsu",
|
|
"renesas,rzg2l-tsu";
|
|
reg = <0 0x10059400 0 0x400>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
|
|
resets = <&cpg R9A07G044_TSU_PRESETN>;
|
|
power-domains = <&cpg>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
sbc: spi@10060000 {
|
|
compatible = "renesas,r9a07g044-rpc-if",
|
|
"renesas,rzg2l-rpc-if";
|
|
reg = <0 0x10060000 0 0x10000>,
|
|
<0 0x20000000 0 0x10000000>,
|
|
<0 0x10070000 0 0x10000>;
|
|
reg-names = "regs", "dirmap", "wbuf";
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
|
|
<&cpg CPG_MOD R9A07G044_SPI_CLK>;
|
|
resets = <&cpg R9A07G044_SPI_RST>;
|
|
power-domains = <&cpg>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cru: video@10830000 {
|
|
compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
|
|
reg = <0 0x10830000 0 0x400>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
|
|
<&cpg CPG_MOD R9A07G044_CRU_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_CRU_ACLK>;
|
|
clock-names = "video", "apb", "axi";
|
|
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
|
|
resets = <&cpg R9A07G044_CRU_PRESETN>,
|
|
<&cpg R9A07G044_CRU_ARESETN>;
|
|
reset-names = "presetn", "aresetn";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
cruparallel: endpoint@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
crucsi2: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&csi2cru>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
csi2: csi2@10830400 {
|
|
compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
|
|
reg = <0 0x10830400 0 0xfc00>;
|
|
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
|
|
<&cpg CPG_MOD R9A07G044_CRU_VCLK>,
|
|
<&cpg CPG_MOD R9A07G044_CRU_PCLK>;
|
|
clock-names = "system", "video", "apb";
|
|
resets = <&cpg R9A07G044_CRU_PRESETN>,
|
|
<&cpg R9A07G044_CRU_CMN_RSTB>;
|
|
reset-names = "presetn", "cmn-rstb";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
csi2cru: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&crucsi2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dsi: dsi@10850000 {
|
|
compatible = "renesas,r9a07g044-mipi-dsi",
|
|
"renesas,rzg2l-mipi-dsi";
|
|
reg = <0 0x10850000 0 0x20000>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "seq0", "seq1", "vin1", "rcv",
|
|
"ferr", "ppi", "debug";
|
|
clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
|
|
<&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
|
|
<&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
|
|
<&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
|
|
<&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
|
|
clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
|
|
resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
|
|
<&cpg R9A07G044_MIPI_DSI_ARESET_N>,
|
|
<&cpg R9A07G044_MIPI_DSI_PRESET_N>;
|
|
reset-names = "rst", "arst", "prst";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vspd: vsp@10870000 {
|
|
compatible = "renesas,r9a07g044-vsp2";
|
|
reg = <0 0x10870000 0 0x10000>;
|
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
|
|
<&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
|
|
<&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
|
|
clock-names = "aclk", "pclk", "vclk";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_LCDC_RESET_N>;
|
|
renesas,fcp = <&fcpvd>;
|
|
};
|
|
|
|
fcpvd: fcp@10880000 {
|
|
compatible = "renesas,r9a07g044-fcpvd",
|
|
"renesas,fcpv";
|
|
reg = <0 0x10880000 0 0x10000>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
|
|
<&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
|
|
<&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
|
|
clock-names = "aclk", "pclk", "vclk";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_LCDC_RESET_N>;
|
|
};
|
|
|
|
cpg: clock-controller@11010000 {
|
|
compatible = "renesas,r9a07g044-cpg";
|
|
reg = <0 0x11010000 0 0x10000>;
|
|
clocks = <&extal_clk>;
|
|
clock-names = "extal";
|
|
#clock-cells = <2>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
sysc: system-controller@11020000 {
|
|
compatible = "renesas,r9a07g044-sysc";
|
|
reg = <0 0x11020000 0 0x10000>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "lpm_int", "ca55stbydone_int",
|
|
"cm33stbyr_int", "ca55_deny";
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pinctrl@11030000 {
|
|
compatible = "renesas,r9a07g044-pinctrl";
|
|
reg = <0 0x11030000 0 0x10000>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&irqc>;
|
|
interrupt-controller;
|
|
gpio-ranges = <&pinctrl 0 0 392>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_GPIO_RSTN>,
|
|
<&cpg R9A07G044_GPIO_PORT_RESETN>,
|
|
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
|
|
};
|
|
|
|
irqc: interrupt-controller@110a0000 {
|
|
compatible = "renesas,r9a07g044-irqc",
|
|
"renesas,rzg2l-irqc";
|
|
#interrupt-cells = <2>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0 0x110a0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
|
|
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
|
|
clock-names = "clk", "pclk";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_IA55_RESETN>;
|
|
};
|
|
|
|
dmac: dma-controller@11820000 {
|
|
compatible = "renesas,r9a07g044-dmac",
|
|
"renesas,rz-dmac";
|
|
reg = <0 0x11820000 0 0x10000>,
|
|
<0 0x11830000 0 0x10000>;
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
|
|
<&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
|
|
clock-names = "main", "register";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_DMAC_ARESETN>,
|
|
<&cpg R9A07G044_DMAC_RST_ASYNC>;
|
|
reset-names = "arst", "rst_async";
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
};
|
|
|
|
gpu: gpu@11840000 {
|
|
compatible = "renesas,r9a07g044-mali",
|
|
"arm,mali-bifrost";
|
|
reg = <0x0 0x11840000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "job", "mmu", "gpu", "event";
|
|
clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
|
|
<&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
|
|
<&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
|
|
clock-names = "gpu", "bus", "bus_ace";
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A07G044_GPU_RESETN>,
|
|
<&cpg R9A07G044_GPU_AXI_RESETN>,
|
|
<&cpg R9A07G044_GPU_ACE_RESETN>;
|
|
reset-names = "rst", "axi_rst", "ace_rst";
|
|
operating-points-v2 = <&gpu_opp_table>;
|
|
};
|
|
|
|
gic: interrupt-controller@11900000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x0 0x11900000 0 0x40000>,
|
|
<0x0 0x11940000 0 0x60000>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
sdhi0: mmc@11c00000 {
|
|
compatible = "renesas,sdhi-r9a07g044",
|
|
"renesas,rcar-gen3-sdhi";
|
|
reg = <0x0 0x11c00000 0 0x10000>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
|
|
<&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
|
|
<&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
|
|
<&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
|
|
clock-names = "core", "clkh", "cd", "aclk";
|
|
resets = <&cpg R9A07G044_SDHI0_IXRST>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi1: mmc@11c10000 {
|
|
compatible = "renesas,sdhi-r9a07g044",
|
|
"renesas,rcar-gen3-sdhi";
|
|
reg = <0x0 0x11c10000 0 0x10000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
|
|
<&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
|
|
<&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
|
|
<&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
|
|
clock-names = "core", "clkh", "cd", "aclk";
|
|
resets = <&cpg R9A07G044_SDHI1_IXRST>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
eth0: ethernet@11c20000 {
|
|
compatible = "renesas,r9a07g044-gbeth",
|
|
"renesas,rzg2l-gbeth";
|
|
reg = <0 0x11c20000 0 0x10000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mux", "fil", "arp_ns";
|
|
phy-mode = "rgmii";
|
|
clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
|
|
<&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
|
|
<&cpg CPG_CORE R9A07G044_CLK_HP>;
|
|
clock-names = "axi", "chi", "refclk";
|
|
resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
|
|
power-domains = <&cpg>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
eth1: ethernet@11c30000 {
|
|
compatible = "renesas,r9a07g044-gbeth",
|
|
"renesas,rzg2l-gbeth";
|
|
reg = <0 0x11c30000 0 0x10000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mux", "fil", "arp_ns";
|
|
phy-mode = "rgmii";
|
|
clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
|
|
<&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
|
|
<&cpg CPG_CORE R9A07G044_CLK_HP>;
|
|
clock-names = "axi", "chi", "refclk";
|
|
resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
|
|
power-domains = <&cpg>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phyrst: usbphy-ctrl@11c40000 {
|
|
compatible = "renesas,r9a07g044-usbphy-ctrl",
|
|
"renesas,rzg2l-usbphy-ctrl";
|
|
reg = <0 0x11c40000 0 0x10000>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
|
|
resets = <&cpg R9A07G044_USB_PRESETN>;
|
|
power-domains = <&cpg>;
|
|
#reset-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@11c50000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0 0x11c50000 0 0x100>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
|
|
resets = <&phyrst 0>,
|
|
<&cpg R9A07G044_USB_U2H0_HRESETN>;
|
|
phys = <&usb2_phy0 1>;
|
|
phy-names = "usb";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci1: usb@11c70000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0 0x11c70000 0 0x100>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
|
|
resets = <&phyrst 1>,
|
|
<&cpg R9A07G044_USB_U2H1_HRESETN>;
|
|
phys = <&usb2_phy1 1>;
|
|
phy-names = "usb";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci0: usb@11c50100 {
|
|
compatible = "generic-ehci";
|
|
reg = <0 0x11c50100 0 0x100>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
|
|
resets = <&phyrst 0>,
|
|
<&cpg R9A07G044_USB_U2H0_HRESETN>;
|
|
phys = <&usb2_phy0 2>;
|
|
phy-names = "usb";
|
|
companion = <&ohci0>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci1: usb@11c70100 {
|
|
compatible = "generic-ehci";
|
|
reg = <0 0x11c70100 0 0x100>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
|
|
resets = <&phyrst 1>,
|
|
<&cpg R9A07G044_USB_U2H1_HRESETN>;
|
|
phys = <&usb2_phy1 2>;
|
|
phy-names = "usb";
|
|
companion = <&ohci1>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2_phy0: usb-phy@11c50200 {
|
|
compatible = "renesas,usb2-phy-r9a07g044",
|
|
"renesas,rzg2l-usb2-phy";
|
|
reg = <0 0x11c50200 0 0x700>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
|
|
resets = <&phyrst 0>;
|
|
#phy-cells = <1>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2_phy1: usb-phy@11c70200 {
|
|
compatible = "renesas,usb2-phy-r9a07g044",
|
|
"renesas,rzg2l-usb2-phy";
|
|
reg = <0 0x11c70200 0 0x700>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
|
|
resets = <&phyrst 1>;
|
|
#phy-cells = <1>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsusb: usb@11c60000 {
|
|
compatible = "renesas,usbhs-r9a07g044",
|
|
"renesas,rza2-usbhs";
|
|
reg = <0 0x11c60000 0 0x10000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
|
|
resets = <&phyrst 0>,
|
|
<&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
|
|
renesas,buswait = <7>;
|
|
phys = <&usb2_phy0 3>;
|
|
phy-names = "usb";
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdt0: watchdog@12800800 {
|
|
compatible = "renesas,r9a07g044-wdt",
|
|
"renesas,rzg2l-wdt";
|
|
reg = <0 0x12800800 0 0x400>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_WDT0_CLK>;
|
|
clock-names = "pclk", "oscclk";
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "wdt", "perrout";
|
|
resets = <&cpg R9A07G044_WDT0_PRESETN>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdt1: watchdog@12800c00 {
|
|
compatible = "renesas,r9a07g044-wdt",
|
|
"renesas,rzg2l-wdt";
|
|
reg = <0 0x12800C00 0 0x400>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
|
|
<&cpg CPG_MOD R9A07G044_WDT1_CLK>;
|
|
clock-names = "pclk", "oscclk";
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "wdt", "perrout";
|
|
resets = <&cpg R9A07G044_WDT1_PRESETN>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ostm0: timer@12801000 {
|
|
compatible = "renesas,r9a07g044-ostm",
|
|
"renesas,ostm";
|
|
reg = <0x0 0x12801000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
|
|
resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ostm1: timer@12801400 {
|
|
compatible = "renesas,r9a07g044-ostm",
|
|
"renesas,ostm";
|
|
reg = <0x0 0x12801400 0x0 0x400>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
|
|
resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ostm2: timer@12801800 {
|
|
compatible = "renesas,r9a07g044-ostm",
|
|
"renesas,ostm";
|
|
reg = <0x0 0x12801800 0x0 0x400>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
|
|
resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&tsu 0>;
|
|
sustainable-power = <717>;
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&target>;
|
|
cooling-device = <&cpu0 0 2>;
|
|
contribution = <1024>;
|
|
};
|
|
};
|
|
|
|
trips {
|
|
sensor_crit: sensor-crit {
|
|
temperature = <125000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
|
|
target: trip-point {
|
|
temperature = <100000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|