Michael Walle 6bdda4b200 board: sl28: set CPO value ... With a 8GiB memory board, it seems that the "very unlikely event" of a DDR initialization with non-optimal values are not really that unlikely. It happens in about every other reboot. As described in erratum A-009942, preset the DEBUG_28 register with an optimal value. The value iself depends on the memory configuration of the board, but the used value seems to work well for all variants. Signed-off-by: Michael Walle <michael@walle.cc>		2022-06-20 15:52:45 +08:00
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cmds.c	global: Convert simple_strtoul() with hex to hextoul()	2021-08-02 13:32:14 -04:00
common.c	board: sl28: add config to enable console output on SER0	2021-04-15 14:22:22 +05:30
ddr.c	board: sl28: set CPO value	2022-06-20 15:52:45 +08:00
Kconfig	board: sl28: add config to enable console output on SER0	2021-04-15 14:22:22 +05:30
MAINTAINERS	board: kontron: sl28: add myself to ls1028a.dtsi maintainers	2021-11-09 17:18:23 +05:30
Makefile	board: sl28: add basic PSCI implementation	2022-04-26 17:13:57 +05:30
psci.c	board: sl28: add basic PSCI implementation	2022-04-26 17:13:57 +05:30
sl28.c	capsule: board: Add information needed for capsule updates	2022-04-15 10:43:18 +02:00
spl.c	board: sl28: add SATA support	2021-02-08 14:01:16 +05:30
spl_atf.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00