u-boot

mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-17 10:18:38 +00:00

History

Tom Rini 6e7df1d151 global: Finish CONFIG -> CFG migration At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>		2023-01-20 12:27:24 -05:00
..
ddr.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
eth.c	global: Finish CONFIG -> CFG migration	2023-01-20 12:27:24 -05:00
Kconfig	nxp: Make board/freescale/common/Kconfig safe to include once in arch/Kconfig	2022-07-05 17:03:02 -04:00
ls1046afrwy.c	global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace	2022-11-10 10:08:55 -05:00
MAINTAINERS	board: ls1046afrwy: Remove Manish Tomar's email	2022-04-26 17:18:39 +05:30
Makefile	armv8: ls1046afrwy: Add support for LS1046AFRWY platform	2019-06-19 12:54:57 +05:30
README	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00

README

Overview
--------
The LS1046A Freeway Board (iFRWY) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS1046A
LayerScape Architecture processor. The FRWY-LS1046A provides SW development
platform for the Freescale LS1046A processor series, with a complete
debugging environment. The FRWY-LS1046A  is lead-free and RoHS-compliant.

LS1046A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
SoC overview.

 FRWY-LS1046A board Overview
 -----------------------
 - SERDES1 Connections, 4 lanes supporting:
      - Lane0: Unused
      - Lane1: Unused
      - Lane2: QSGMII
      - Lane3: Unused
 - SERDES2 Connections, 4 lanes supporting:
      - Lane0: Unused
      - Lane1: PCIe3 with PCIe x1 slot
      - Lane2: Unused
      - Lane3: PCIe3 with PCIe x1 slot
 - DDR Controller
     - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
 -IFC/Local Bus
    - One 512 MB NAND flash with ECC support
 - USB 3.0
    - Two Type A port
 - SDHC: connects directly to a full microSD slot
 - QSPI: 64 MB high-speed flash Memory for boot code and storage
 - 4 I2C controllers
 - UART
   - Two 4-pin serial ports at up to 115.2 Kbit/s
   - Two DB9 D-Type connectors supporting one Serial port each
 - ARM JTAG support

Memory map from core's view
----------------------------
Start Address	 End Address	 Description		Size
0x00_0000_0000 - 0x00_000F_FFFF  Secure Boot ROM	1MB
0x00_0100_0000 - 0x00_0FFF_FFFF  CCSRBAR		240MB
0x00_1000_0000 - 0x00_1000_FFFF  OCRAM0			64KB
0x00_1001_0000 - 0x00_1001_FFFF  OCRAM1			64KB
0x00_2000_0000 - 0x00_20FF_FFFF  DCSR			16MB
0x00_7E80_0000 - 0x00_7E80_FFFF  IFC - NAND Flash	64KB
0x00_7FB0_0000 - 0x00_7FB0_0FFF  IFC - CPLD		4KB
0x00_8000_0000 - 0x00_FFFF_FFFF  DRAM1			2GB
0x05_0000_0000 - 0x05_07FF_FFFF  QMAN S/W Portal	128M
0x05_0800_0000 - 0x05_0FFF_FFFF  BMAN S/W Portal	128M
0x08_8000_0000 - 0x09_FFFF_FFFF  DRAM2			6GB
0x40_0000_0000 - 0x47_FFFF_FFFF  PCI Express1		32G
0x48_0000_0000 - 0x4F_FFFF_FFFF  PCI Express2		32G
0x50_0000_0000 - 0x57_FFFF_FFFF  PCI Express3		32G

QSPI flash map:
Start Address    End Address     Description		Size
0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI + BL2	1MB
0x00_4010_0000 - 0x00_404F_FFFF  FIP Image
				  (Bl31 + BL32(optee.
				  bin) + Bl33(uboot)
				  + headers for secure
				  boot)			4MB
0x00_4050_0000 - 0x00_405F_FFFF  Boot Firmware Env	1MB
0x00_4060_0000 - 0x00_408F_FFFF  Secure boot headers	3MB
0x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
0x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
0x00_409C_0000 - 0x00_409F_FFFF  Reserved		256KB
0x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB

Booting Options
---------------
a) QSPI boot
b) microSD boot