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15ca9ebb07
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This PHY initialization should be handled from Xilinx USB core as the prerequisite register configurations are done here only. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
541 lines
9.6 KiB
Text
541 lines
9.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP ZCU104
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*
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* (C) Copyright 2017 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP ZCU104 RevA";
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compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem3;
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i2c0 = &i2c1;
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mmc0 = &sdhci1;
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nvmem0 = &eeprom;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &dcc;
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spi0 = &qspi;
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usb0 = &usb0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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clock_8t49n287_5: clk125 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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clock_8t49n287_2: clk26 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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clock_8t49n287_3: clk27 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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&can1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1_default>;
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};
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&dcc {
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status = "okay";
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gem3 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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phy0: ethernet-phy@c {
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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&gpio {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
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/* Another connection to this bus via PL i2c via PCA9306 - u45 */
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i2c-mux@74 { /* u34 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/*
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* IIC_EEPROM 1kB memory which uses 256B blocks
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* where every block has different address.
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* 0 - 256B address 0x54
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* 256B - 512B address 0x55
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* 512B - 768B address 0x56
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* 768B - 1024B address 0x57
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*/
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eeprom: eeprom@54 { /* u23 */
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compatible = "atmel,24c08";
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reg = <0x54>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* 8T49N287 - u182 */
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
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compatible = "infineon,irps5401";
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reg = <0x43>; /* pmbus / i2c 0x13 */
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};
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irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
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compatible = "infineon,irps5401";
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reg = <0x44>; /* pmbus / i2c 0x14 */
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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tca6416_u97: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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/*
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* IRQ not connected
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* Lines:
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* 0 - IRPS5401_ALERT_B
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* 1 - HDMI_8T49N241_INT_ALM
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* 2 - MAX6643_OT_B
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* 3 - MAX6643_FANFAIL_B
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* 5 - IIC_MUX_RESET_B
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* 6 - GEM3_EXP_RESET_B
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* 7 - FMC_LPC_PRSNT_M2C_B
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* 4, 10 - 17 - not connected
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*/
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};
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};
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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};
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i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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};
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/* 3, 6 not connected */
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};
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};
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&pinctrl0 {
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status = "okay";
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pinctrl_can1_default: can1-default {
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mux {
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function = "can1";
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groups = "can1_6_grp";
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};
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conf {
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groups = "can1_6_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO25";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO24";
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bias-disable;
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};
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};
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pinctrl_i2c1_default: i2c1-default {
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mux {
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groups = "i2c1_4_grp";
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function = "i2c1";
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};
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conf {
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groups = "i2c1_4_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio {
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mux {
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groups = "gpio0_16_grp", "gpio0_17_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_16_grp", "gpio0_17_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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};
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pinctrl_gem3_default: gem3-default {
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mux {
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function = "ethernet3";
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groups = "ethernet3_0_grp";
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};
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conf {
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groups = "ethernet3_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
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"MIO75";
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bias-high-impedance;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
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"MIO69";
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bias-disable;
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low-power-enable;
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};
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mux-mdio {
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function = "mdio3";
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groups = "mdio3_0_grp";
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};
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conf-mdio {
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groups = "mdio3_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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};
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pinctrl_sdhci1_default: sdhci1-default {
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mux {
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groups = "sdio1_0_grp";
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function = "sdio1";
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};
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conf {
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groups = "sdio1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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drive-strength = <12>;
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};
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mux-cd {
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groups = "sdio1_cd_0_grp";
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function = "sdio1_cd";
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};
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conf-cd {
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groups = "sdio1_cd_0_grp";
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bias-high-impedance;
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_uart0_default: uart0-default {
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mux {
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groups = "uart0_4_grp";
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function = "uart0";
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};
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conf {
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groups = "uart0_4_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO18";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO19";
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bias-disable;
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};
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};
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_5_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_5_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO21";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO20";
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bias-disable;
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};
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};
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pinctrl_usb0_default: usb0-default {
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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conf {
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groups = "usb0_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO52", "MIO53", "MIO55";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
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"MIO60", "MIO61", "MIO62", "MIO63";
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bias-disable;
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};
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};
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};
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&psgtr {
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status = "okay";
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/* nc, sata, usb3, dp */
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clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
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clock-names = "ref1", "ref2", "ref3";
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>; /* Based on DC1 spec */
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partition@0 { /* for testing purpose */
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@100000 { /* for testing purpose */
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@600000 { /* for testing purpose */
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@620000 { /* for testing purpose */
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label = "qspi-rootfs";
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reg = <0x620000 0x5E0000>;
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};
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};
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};
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&rtc {
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status = "okay";
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};
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&sata {
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status = "okay";
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/* SATA OOB timing settings */
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ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
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ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
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ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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phy-names = "sata-phy";
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phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
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};
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/* SD1 with level shifter */
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&sdhci1 {
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status = "okay";
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no-1-8-v;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci1_default>;
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xlnx,mio-bank = <1>;
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disable-wp;
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};
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&uart0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0_default>;
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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/* ULPI SMSC USB3320 */
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&usb0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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phy-names = "usb3-phy";
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phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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maximum-speed = "super-speed";
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};
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&watchdog0 {
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status = "okay";
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};
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&xilinx_ams {
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status = "okay";
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};
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&ams_ps {
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status = "okay";
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};
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&ams_pl {
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status = "okay";
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};
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&zynqmp_dpdma {
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status = "okay";
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};
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&zynqmp_dpsub {
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status = "okay";
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phy-names = "dp-phy0", "dp-phy1";
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phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
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<&psgtr 0 PHY_TYPE_DP 1 3>;
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};
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