mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 05:04:26 +00:00
2d4b87f867
Sync the mx7ulp device tree related files with the one from NXP U-Boot vendor tree (imx_v2019.04_4.19.35_1.0.0). The mainline support for i.MX7ULP is very premature at this stage. We should probably re-sync with mainline Linux dts when it gets in better shape, but for now sync with the U-Boot vendor code. Signed-off-by: Fabio Estevam <festevam@gmail.com>
618 lines
16 KiB
Text
618 lines
16 KiB
Text
/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/imx7ulp-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "skeleton.dtsi"
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#include "imx7ulp-pinfunc.h"
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/ {
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interrupt-parent = <&intc>;
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aliases {
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gpio0 = &gpio4;
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gpio1 = &gpio5;
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gpio2 = &gpio0;
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gpio3 = &gpio1;
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gpio4 = &gpio2;
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gpio5 = &gpio3;
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mmc0 = &usdhc0;
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mmc1 = &usdhc1;
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serial0 = &lpuart4;
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serial1 = &lpuart5;
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serial2 = &lpuart6;
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serial3 = &lpuart7;
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usbphy0 = &usbphy1;
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usb0 = &usbotg1;
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i2c4 = &lpi2c4;
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i2c5 = &lpi2c5;
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i2c6 = &lpi2c6;
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i2c7 = &lpi2c7;
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spi0 = &qspi1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0xC000000>;
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alignment = <0x2000>;
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linux,cma-default;
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};
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rpmsg_reserved: rpmsg@9FFF0000 {
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no-map;
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reg = <0x9FF00000 0x100000>;
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};
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};
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intc: interrupt-controller@40021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x40021000 0x1000>,
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<0x40022000 0x100>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ckil: clock@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "ckil";
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};
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osc: clock@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc";
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};
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sirc: clock@2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <16000000>;
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clock-output-names = "sirc";
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};
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firc: clock@3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "firc";
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};
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upll: clock@4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <480000000>;
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clock-output-names = "upll";
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};
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mpll: clock@5 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <480000000>;
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clock-output-names = "mpll";
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};
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};
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sram: sram@20000000 {
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compatible = "fsl,lpm-sram";
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reg = <0x1fffc000 0x4000>;
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};
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ahbbridge0: ahb-bridge0@40000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40000000 0x800000>;
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ranges;
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edma0: dma-controller@40080000 {
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#dma-cells = <2>;
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compatible = "nxp,imx7ulp-edma";
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reg = <0x40080000 0x2000>,
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<0x40210000 0x1000>;
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dma-channels = <32>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dma", "dmamux0";
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clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
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};
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mu: mu@40220000 {
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compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu";
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reg = <0x40220000 0x1000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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nmi: nmi@40220000 {
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compatible = "fsl,imx7ulp-nmi";
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reg = <0x40220000 0x1000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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rpmsg: rpmsg{
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compatible = "fsl,imx7ulp-rpmsg";
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memory-region = <&rpmsg_reserved>;
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status = "disabled";
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};
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snvs: snvs@40230000 {
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compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
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reg = <0x40230000 0x10000>;
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snvs_rtc: snvs-rtc-lp{
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compatible = "fsl,sec-v4.0-mon-rtc-lp";
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regmap =<&snvs>;
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offset = <0x34>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "snvs-rtc";
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clocks = <&clks IMX7ULP_CLK_SNVS>;
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};
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};
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tpm5: tpm@40260000 {
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compatible = "fsl,imx7ulp-tpm";
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reg = <0x40260000 0x1000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPTPM5>;
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};
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lpit: 1@40270000 {
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compatible = "fsl,imx-lpit";
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reg = <0x40270000 0x1000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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/* clocks = <&lpclk>;*/
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clocks = <&clks IMX7ULP_CLK_LPIT1>;
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assigned-clock-rates = <48000000>;
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assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
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};
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lpi2c4: lpi2c4@402B0000 {
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compatible = "fsl,imx7ulp-lpi2c";
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reg = <0x402B0000 0x10000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPI2C4>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpi2c5: lpi2c4@402C0000 {
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compatible = "fsl,imx7ulp-lpi2c";
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reg = <0x402C0000 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPI2C5>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpspi2: lpspi@40290000 {
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compatible = "fsl,imx7ulp-spi";
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reg = <0x40290000 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPSPI2>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpspi3: lpspi@402A0000 {
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compatible = "fsl,imx7ulp-spi";
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reg = <0x402A0000 0x10000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPSPI3>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpuart4: serial@402D0000 {
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compatible = "fsl,imx7ulp-lpuart";
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reg = <0x402D0000 0x1000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPUART4>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
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assigned-clock-rates = <24000000>;
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status = "disabled";
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};
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lpuart5: serial@402E0000 {
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compatible = "fsl,imx7ulp-lpuart";
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reg = <0x402E0000 0x1000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPUART5>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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dmas = <&edma0 0 20>, <&edma0 0 19>;
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dma-names = "tx","rx";
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status = "disabled";
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};
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usbotg1: usb@40330000 {
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compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb",
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"fsl,imx27-usb";
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reg = <0x40330000 0x200>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_USB0>;
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fsl,usbphy = <&usbphy1>;
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fsl,usbmisc = <&usbmisc1 0>;
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ahb-burst-config = <0x0>;
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tx-burst-size-dword = <0x8>;
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rx-burst-size-dword = <0x8>;
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status = "disabled";
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};
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usbmisc1: usbmisc@40330200 {
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#index-cells = <1>;
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compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
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"fsl,imx6q-usbmisc";
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reg = <0x40330200 0x200>;
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};
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usbphy1: usbphy@0x40350000 {
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compatible = "fsl,imx7ulp-usbphy",
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"fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
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reg = <0x40350000 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_USB_PHY>;
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nxp,sim = <&sim>;
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};
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usdhc0: usdhc@40370000 {
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compatible = "fsl,imx7ulp-usdhc";
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reg = <0x40370000 0x10000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&clks IMX7ULP_CLK_NIC1_DIV>,
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<&clks IMX7ULP_CLK_USDHC0>;
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clock-names ="ipg", "ahb", "per";
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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usdhc1: usdhc@40380000 {
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compatible = "fsl,imx7ulp-usdhc";
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reg = <0x40380000 0x10000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&clks IMX7ULP_CLK_NIC1_DIV>,
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<&clks IMX7ULP_CLK_USDHC1>;
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clock-names ="ipg", "ahb", "per";
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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wdog1: wdog@403D0000 {
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compatible = "fsl,imx7ulp-wdt";
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reg = <0x403D0000 0x10000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_WDG1>;
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assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
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assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
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/*
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* As the 1KHz LPO clock rate is not trimed,the actually clock
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* is about 667Hz, so the init timeout 60s should set 40*1000
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* in the TOVAL register.
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*/
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timeout-sec = <40>;
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};
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wdog2: wdog@40430000 {
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compatible = "fsl,imx7ulp-wdt";
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reg = <0x40430000 0x10000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_WDG2>;
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assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
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assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
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timeout-sec = <40>;
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};
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clks: scg1@403E0000 {
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compatible = "fsl,imx7ulp-scg1";
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reg = <0x403E0000 0x10000>;
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clocks = <&ckil>, <&osc>, <&sirc>,
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<&firc>, <&upll>, <&mpll>;
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clock-names = "ckil", "osc", "sirc",
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"firc", "upll", "mpll";
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#clock-cells = <1>;
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assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
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<&clks IMX7ULP_CLK_USDHC1>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
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<&clks IMX7ULP_CLK_NIC1_DIV>;
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};
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pcc2: pcc2@403F0000 {
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compatible = "fsl,imx7ulp-pcc2";
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reg = <0x403F0000 0x10000>;
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};
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pmc1: pmc1@40400000 {
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compatible = "fsl,imx7ulp-pmc1";
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reg = <0x40400000 0x1000>;
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};
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smc1: smc1@40410000 {
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compatible = "fsl,imx7ulp-smc1";
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reg = <0x40410000 0x1000>;
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};
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};
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ahbbridge1: ahb-bridge1@40800000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40800000 0x800000>;
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ranges;
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lpi2c6: lpi2c6@40A40000 {
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compatible = "fsl,imx7ulp-lpi2c";
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reg = <0x40A40000 0x10000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPI2C6>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpi2c7: lpi2c7@40A50000 {
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compatible = "fsl,imx7ulp-lpi2c";
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reg = <0x40A50000 0x10000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPI2C7>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
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assigned-clock-rates = <48000000>;
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status = "disabled";
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};
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lpuart6: serial@40A60000 {
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compatible = "fsl,imx7ulp-lpuart";
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reg = <0x40A60000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPUART6>;
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clock-names = "ipg";
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assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
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assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
|
assigned-clock-rates = <48000000>;
|
|
dmas = <&edma0 0 22>, <&edma0 0 21>;
|
|
dma-names = "tx","rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart7: serial@40A70000 {
|
|
compatible = "fsl,imx7ulp-lpuart";
|
|
reg = <0x40A70000 0x1000>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7ULP_CLK_LPUART7>;
|
|
clock-names = "ipg";
|
|
assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
|
|
assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
|
|
assigned-clock-rates = <50000000>;
|
|
dmas = <&edma0 0 24>, <&edma0 0 23>;
|
|
dma-names = "tx","rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
lcdif: lcdif@40AA0000 {
|
|
compatible = "fsl,imx7ulp-lcdif";
|
|
reg = <0x40aa0000 0x10000>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7ULP_CLK_DUMMY>,
|
|
<&clks IMX7ULP_CLK_LCDIF>,
|
|
<&clks IMX7ULP_CLK_DUMMY>;
|
|
clock-names = "axi", "pix", "disp_axi";
|
|
status = "disabled";
|
|
};
|
|
|
|
mipi_dsi: mipi_dsi@40A90000 {
|
|
compatible = "fsl,imx7ulp-mipi-dsi";
|
|
reg = <0x40A90000 0x10000>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7ULP_CLK_DSI>;
|
|
clock-names = "mipi_dsi_clk";
|
|
sim = <&sim>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmdc: mmdc@40ab0000 {
|
|
compatible = "fsl,imx7ulp-mmdc";
|
|
reg = <0x40ab0000 0x4000>;
|
|
};
|
|
|
|
pcc3: pcc3@40B30000 {
|
|
compatible = "fsl,imx7ulp-pcc3";
|
|
reg = <0x40B30000 0x10000>;
|
|
};
|
|
|
|
iomuxc: iomuxc@4103D000 {
|
|
compatible = "fsl,imx7ulp-iomuxc-0";
|
|
reg = <0x4103D000 0x1000>;
|
|
fsl,mux_mask = <0xf00>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iomuxc1: iomuxc1@40ac0000 {
|
|
compatible = "fsl,imx7ulp-iomuxc-1";
|
|
reg = <0x40ac0000 0x1000>;
|
|
fsl,mux_mask = <0xf00>;
|
|
};
|
|
|
|
gpio4: gpio@4103f000 {
|
|
compatible = "fsl,imx7ulp-gpio";
|
|
reg = <0x4103f000 0x1000 0x4100F000 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 0 32>;
|
|
};
|
|
|
|
gpio5: gpio@41040000 {
|
|
compatible = "fsl,imx7ulp-gpio";
|
|
reg = <0x41040000 0x1000 0x4100F040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 32 32>;
|
|
};
|
|
|
|
gpio0: gpio@40ae0000 {
|
|
compatible = "fsl,imx7ulp-gpio";
|
|
reg = <0x40ae0000 0x1000 0x400F0000 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc1 0 0 32>;
|
|
};
|
|
|
|
gpio1: gpio@40af0000 {
|
|
compatible = "fsl,imx7ulp-gpio";
|
|
reg = <0x40af0000 0x1000 0x400F0040 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc1 0 32 32>;
|
|
};
|
|
|
|
gpio2: gpio@40b00000 {
|
|
compatible = "fsl,imx7ulp-gpio";
|
|
reg = <0x40b00000 0x1000 0x400F0080 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc1 0 64 32>;
|
|
};
|
|
|
|
gpio3: gpio@40b10000 {
|
|
compatible = "fsl,imx7ulp-gpio";
|
|
reg = <0x40b10000 0x1000 0x400F00c0 0x40>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc1 0 96 32>;
|
|
};
|
|
|
|
pmc0: pmc0@410a1000 {
|
|
compatible = "fsl,imx7ulp-pmc0";
|
|
reg = <0x410a1000 0x1000>;
|
|
};
|
|
|
|
sim: sim@410a3000 {
|
|
compatible = "fsl,imx7ulp-sim", "syscon";
|
|
reg = <0x410a3000 0x1000>;
|
|
};
|
|
|
|
qspi1: qspi@410A5000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx7ulp-qspi";
|
|
reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX7ULP_CLK_DUMMY>,
|
|
<&clks IMX7ULP_CLK_DUMMY>;
|
|
clock-names = "qspi_en", "qspi";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpu: gpu@41800000 {
|
|
compatible = "fsl,imx6q-gpu";
|
|
reg = <0x41800000 0x80000>, <0x41880000 0x80000>,
|
|
<0x60000000 0x40000000>, <0x0 0x4000000>;
|
|
reg-names = "iobase_3d", "iobase_2d",
|
|
"phys_baseaddr", "contiguous_mem";
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_3d", "irq_2d";
|
|
clocks = <&clks IMX7ULP_CLK_GPU3D>,
|
|
<&clks IMX7ULP_CLK_NIC1_DIV>,
|
|
<&clks IMX7ULP_CLK_GPU_DIV>,
|
|
<&clks IMX7ULP_CLK_GPU2D>,
|
|
<&clks IMX7ULP_CLK_NIC1_DIV>,
|
|
<&clks IMX7ULP_CLK_NIC1_DIV>;
|
|
clock-names = "gpu3d_clk", "gpu3d_shader_clk",
|
|
"gpu3d_axi_clk", "gpu2d_clk",
|
|
"gpu2d_shader_clk", "gpu2d_axi_clk";
|
|
};
|
|
};
|
|
|
|
imx_ion {
|
|
compatible = "fsl,mxc-ion";
|
|
fsl,heap-id = <0>;
|
|
};
|
|
};
|