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https://github.com/AsahiLinux/u-boot
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f29eaadeb5
This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
166 lines
3.8 KiB
Text
166 lines
3.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*/
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#undef CP110_NAME
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#undef CP110_NUM
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#undef CP110_PCIE_MEM_SIZE
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#undef CP110_PCIEx_CPU_MEM_BASE
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#undef CP110_PCIEx_BUS_MEM_BASE
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/* CP110-1 Settings */
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#define CP110_NAME cp1
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#define CP110_NUM 1
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#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
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#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
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#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
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#include "armada-cp110.dtsi"
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/ {
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model = "Marvell CN9131 development board";
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compatible = "marvell,cn9131-db";
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aliases {
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gpio3 = &cp1_gpio0;
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gpio4 = &cp1_gpio1;
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};
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cp1 {
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config-space {
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cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_xhci0_vbus_pins>;
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regulator-name = "cp1-xhci0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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startup-delay-us = <100000>;
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regulator-force-boot-off;
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gpio = <&cp1_gpio0 3 GPIO_ACTIVE_HIGH>;
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};
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cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
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compatible = "regulator-fixed";
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regulator-min-microamp = <900000>;
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regulator-max-microamp = <900000>;
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regulator-force-boot-off;
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gpio = <&cp1_gpio0 2 GPIO_ACTIVE_HIGH>;
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};
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cp1_pcie_reset_pins: cp1-pcie-reset-pins {
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marvell,pins = <0>;
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marvell,function = <0>;
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};
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};
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};
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};
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&cp1_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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/* CON40 */
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&cp1_pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_pcie_reset_pins>;
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marvell,reset-gpio = <&cp1_gpio0 0 GPIO_ACTIVE_LOW>;
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status = "okay";
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num-lanes = <2>;
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/* non-prefetchable memory */
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ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
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};
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&cp1_pinctl {
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compatible = "marvell,mvebu-pinctrl",
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"marvell,cp115-standalone-pinctrl";
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bank-name ="cp1-110";
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/* MPP Bus:
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* [0-12] GPIO
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* [13-16] SPI1
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* [17-27] GPIO (Default)
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* [28] SATA1_PRESENT_ACTIVEn
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* [29-34] GPIO (Default)
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* [35-36] xSMI
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* [37-38] I2C0
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* [39-62] GPIO
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x3 0x3 0x3 0x3 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x0
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0x0 0x0 0x0 0x0 0x0 0x7 0x7 0x2 0x2 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 >;
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cp1_i2c0_pins: cp1-i2c-pins-0 {
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marvell,pins = < 37 38 >;
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marvell,function = <2>;
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};
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cp1_spi0_pins: cp1-spi-pins-0 {
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marvell,pins = < 13 14 15 16 >;
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marvell,function = <3>;
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};
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cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
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marvell,pins = <3>;
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marvell,function = <0>;
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};
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};
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/* CON32 */
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&cp1_sata0 {
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status = "okay";
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};
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/* U24 */
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&cp1_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_spi0_pins>;
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reg = <0x700680 0x50>, /* control */
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<0x2000000 0x1000000>, /* CS0 */
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<0 0xffffffff>, /* CS1 */
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<0 0xffffffff>, /* CS2 */
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<0 0xffffffff>; /* CS3 */
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status = "okay";
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spi-flash@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor", "spi-flash";
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reg = <0x0>;
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/* On-board MUX does not allow higher frequencies */
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spi-max-frequency = <40000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x200000>;
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};
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partition@400000 {
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label = "Filesystem";
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reg = <0x200000 0xe00000>;
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};
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};
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};
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};
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/* CON58 */
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&cp1_usb3_1 {
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vbus-supply = <&cp1_reg_usb3_vbus0>;
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current-limiter = <&cp1_reg_usb3_current_lim0>;
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vbus-disable-delay = <500>;
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status = "okay";
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};
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&cp1_utmi1 {
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status = "okay";
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};
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