mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 05:04:26 +00:00
88426bd6b0
Since mvpp2 is using the new mdio driver and the cp110 has been synced with the linux upstream, the mdio has to enabled in the device tree file. This is missing for some device tree files and therefore the network cards do not come online. Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de> Reviewed-by: Stefan Roese <sr@denx.de>
324 lines
6.4 KiB
Text
324 lines
6.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 SolidRun ltd
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*/
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#include "armada-8040.dtsi"
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/ {
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model = "ClearFog-GT-8K";
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compatible = "solidrun,clearfog-gt-8k",
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"marvell,armada8040";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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i2c0 = &cp0_i2c0;
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i2c1 = &cp0_i2c1;
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spi0 = &cp1_spi1;
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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simple-bus {
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compatible = "simple-bus";
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reg_usb3h0_vbus: usb3-vbus0 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_xhci_vbus_pins>;
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regulator-name = "reg-usb3h0-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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startup-delay-us = <300000>;
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shutdown-delay-us = <500000>;
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regulator-force-boot-off;
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gpio = <&cp0_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&ap_pinctl {
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/*
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* MPP Bus:
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* eMMC [0-10]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 1 1 1 1 1 1 1 1 1 1
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1 3 0 0 0 0 0 0 0 3 >;
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};
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/* on-board eMMC */
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&ap_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&ap_emmc_pins>;
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bus-width = <8>;
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status = "okay";
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};
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&cp0_pinctl {
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/*
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* MPP Bus:
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* [0-31] = 0xff: Keep default CP0_shared_pins:
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* [11] CLKOUT_MPP_11 (out)
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* [23] LINK_RD_IN_CP2CP (in)
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* [25] CLKOUT_MPP_25 (out)
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* [29] AVS_FB_IN_CP2CP (in)
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* [32, 33, 34] pci0/1/2 reset
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* [35-38] CP0 I2C1 and I2C0
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* [39] GPIO reset button
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* [40,41] LED0 and LED1
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* [43] 1512 phy reset
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* [47] USB VBUS EN (active low)
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* [48] FAN PWM
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* [49] SFP+ present signal
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* [50] TPM interrupt
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* [51] WLAN0 disable
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* [52] WLAN1 disable
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* [53] LTE disable
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* [54] NFC reset
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* [55] Micro SD card detect
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* [56-61] Micro SD
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0 0 0 0 2 2 2 2 0
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0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0xe 0xe 0xe 0xe
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0xe 0xe 0 >;
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cp0_pcie_reset_pins: cp0-pcie-reset-pins {
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marvell,pins = < 32 >;
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marvell,function = <0>;
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};
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cp0_xhci_vbus_pins: cp0-xhci-vbus-pins {
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marvell,pins = < 47 >;
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marvell,function = <0>;
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};
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cp1_1g_phy_reset: cp1-1g-phy-reset {
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marvell,pins = < 43 >;
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marvell,function = <0>;
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};
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};
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/* uSD slot */
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&cp0_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sdhci_pins>;
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bus-width = <4>;
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status = "okay";
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};
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&cp0_pcie0 {
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num-lanes = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_pcie_reset_pins>;
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marvell,reset-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&cp0_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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&cp0_i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c1_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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&cp0_sata0 {
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status = "okay";
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};
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&cp0_comphy {
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/*
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* CP0 Serdes Configuration:
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* Lane 0: PCIe0 (x1)
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* Lane 1: Not connected
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* Lane 2: SFI0 (10G)
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* Lane 3: Not connected
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* Lane 4: USB 3.0 host port1 (can be PCIe)
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* Lane 5: Not connected
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*/
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phy0 {
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phy-type = <COMPHY_TYPE_PEX0>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_UNCONNECTED>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SFI0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_UNCONNECTED>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_USB3_HOST1>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_UNCONNECTED>;
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};
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};
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&cp0_ethernet {
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pinctrl-names = "default";
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status = "okay";
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};
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/* 10G SFI SFP */
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&cp0_eth0 {
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status = "okay";
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phy-mode = "sfi";
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};
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&cp1_sata0 {
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status = "okay";
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};
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&cp1_usb3_0 {
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vbus-supply = <®_usb3h0_vbus>;
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status = "okay";
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};
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&cp1_utmi0 {
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status = "okay";
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};
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&cp1_pinctl {
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/*
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* MPP Bus:
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* [0-5] TDM
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* [6] VHV Enable
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* [7] CP1 SPI0 CSn1 (FXS)
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* [8] CP1 SPI0 CSn0 (TPM)
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* [9.11]CP1 SPI0 MOSI/MISO/CLK
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* [13] CP1 SPI1 MISO (TDM and SPI ROM shared)
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* [14] CP1 SPI1 CS0n (64Mb SPI ROM)
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* [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)
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* [16] CP1 SPI1 CLK (TDM and SPI ROM shared)
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* [24] Topaz switch reset
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* [26] Buzzer
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* [27] CP1 SMI MDIO
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* [28] CP1 SMI MDC
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* [29] CP0 10G SFP TX Disable
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* [30] WPS button
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* [31] Front panel button
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* [32-62] = 0xff: Keep default CP1_shared_pins:
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x0 0x4 0x4 0x4
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0x4 0x4 0x0 0x3 0x3 0x3 0x3 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x8 0x8 0x0
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0x0 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 0xff>;
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};
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&cp1_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_spi1_pins>;
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status = "okay";
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spi-flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x200000>;
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};
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partition@200000 {
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label = "Filesystem";
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reg = <0x200000 0xce0000>;
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};
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};
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};
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};
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&cp1_comphy {
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/*
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* CP1 Serdes Configuration:
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* Lane 0: SATA 1 (RX swapped). Can be PCIe0
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* Lane 1: Not used
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* Lane 2: USB HOST 0
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* Lane 3: SGMII1 - Connected to 1512 port
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* Lane 4: Not used
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* Lane 5: SGMII2 - Connected to Topaz switch
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*/
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phy0 {
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phy-type = <COMPHY_TYPE_SATA1>;
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phy-invert = <COMPHY_POLARITY_RXD_INVERT>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_UNCONNECTED>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_USB3_HOST0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_SGMII1>;
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phy-speed = <COMPHY_SPEED_1_25G>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_UNCONNECTED>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SGMII2>;
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phy-speed = <COMPHY_SPEED_3_125G>;
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};
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};
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&cp1_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&cp1_ethernet {
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_1g_phy_reset>;
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status = "okay";
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};
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/* 1G SGMII */
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&cp1_eth1 {
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status = "okay";
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phy-mode = "sgmii";
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phy = <&phy0>;
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phy-reset-gpios = <&cp0_gpio1 11 GPIO_ACTIVE_LOW>;
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};
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/* 2.5G to Topaz switch */
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&cp1_eth2 {
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status = "okay";
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phy-mode = "sgmii";
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phy-speed = <2500>;
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phy-reset-gpios = <&cp1_gpio0 24 GPIO_ACTIVE_LOW>;
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};
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