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254887a57e
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.
T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
- Two on-board 10M/100M/1G bps RGMII ports
- Two 10Gbps XFI with on-board SFP+ cage
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
- Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
- 8 lanes up to 10.3125GHz
- Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
- 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
- Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
voltage translators
- I2C:
- Four I2C controllers.
- UART:
- Dual 4-pins UART serial ports
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
146 lines
4.9 KiB
C
146 lines
4.9 KiB
C
/*
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* Copyright 2008-2013 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* TLB 1 */
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/* *I*** - Covers boot page */
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
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/*
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* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
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* SRAM is at 0xfff00000, it covered the 0xfffff000.
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_1M, 1),
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#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
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/*
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* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
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* space is at 0xfff00000, it covered the 0xfffff000.
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
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CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
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0, 0, BOOKE_PAGESZ_1M, 1),
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#else
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_4K, 1),
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#endif
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_16M, 1),
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/* *I*G* - Flash, localbus */
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/* This will be changed to *I*G* after relocation to RAM. */
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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/* *I*G* - PCIe 1, 0x80000000 */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_512M, 1),
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/* *I*G* - PCIe 2, 0xa0000000 */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_256M, 1),
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/* *I*G* - PCIe 3, 0xb0000000 */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_256M, 1),
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/* *I*G* - PCIe 4, 0xc0000000 */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_256M, 1),
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/* *I*G* - PCI I/O */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 7, BOOKE_PAGESZ_256K, 1),
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/* Bman/Qman */
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#ifdef CONFIG_SYS_BMAN_MEM_PHYS
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SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 9, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
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CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 10, BOOKE_PAGESZ_16M, 1),
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#endif
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#ifdef CONFIG_SYS_QMAN_MEM_PHYS
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SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 11, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
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CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 12, BOOKE_PAGESZ_16M, 1),
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#endif
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 13, BOOKE_PAGESZ_32M, 1),
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#endif
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#ifdef CONFIG_SYS_NAND_BASE
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/*
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* *I*G - NAND
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* entry 14 and 15 has been used hard coded, they will be disabled
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* in cpu_init_f, so we use entry 16 for nand.
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 16, BOOKE_PAGESZ_64K, 1),
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#endif
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#ifdef QIXIS_BASE_PHYS
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SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 17, BOOKE_PAGESZ_4K, 1),
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#endif
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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/*
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* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
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* fetching ucode and ENV from master
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
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CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
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0, 18, BOOKE_PAGESZ_1M, 1),
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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