mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 11:18:28 +00:00
a5fd13ad19
Signed-off-by: John Haechten <john.haechten@microsemi.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
508 lines
15 KiB
C
508 lines
15 KiB
C
/*
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* Microsemi PHY drivers
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*
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* SPDX-License-Identifier: The MIT License (MIT)
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*
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* Copyright (c) 2016 Microsemi Corporation
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*
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* Author: John Haechten
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*
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*/
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#include <miiphy.h>
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#include <bitfield.h>
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/* Microsemi PHY ID's */
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#define PHY_ID_VSC8530 0x00070560
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#define PHY_ID_VSC8531 0x00070570
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#define PHY_ID_VSC8540 0x00070760
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#define PHY_ID_VSC8541 0x00070770
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/* Microsemi VSC85xx PHY Register Pages */
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#define MSCC_EXT_PAGE_ACCESS 31 /* Page Access Register */
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#define MSCC_PHY_PAGE_STD 0x0000 /* Standard registers */
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#define MSCC_PHY_PAGE_EXT1 0x0001 /* Extended registers - page 1 */
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#define MSCC_PHY_PAGE_EXT2 0x0002 /* Extended registers - page 2 */
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#define MSCC_PHY_PAGE_EXT3 0x0003 /* Extended registers - page 3 */
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#define MSCC_PHY_PAGE_EXT4 0x0004 /* Extended registers - page 4 */
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#define MSCC_PHY_PAGE_GPIO 0x0010 /* GPIO registers */
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#define MSCC_PHY_PAGE_TEST 0x2A30 /* TEST Page registers */
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#define MSCC_PHY_PAGE_TR 0x52B5 /* Token Ring Page registers */
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/* Std Page Register 28 - PHY AUX Control/Status */
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#define MIIM_AUX_CNTRL_STAT_REG 28
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#define MIIM_AUX_CNTRL_STAT_ACTIPHY_TO (0x0004)
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#define MIIM_AUX_CNTRL_STAT_F_DUPLEX (0x0020)
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#define MIIM_AUX_CNTRL_STAT_SPEED_MASK (0x0018)
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#define MIIM_AUX_CNTRL_STAT_SPEED_POS (3)
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#define MIIM_AUX_CNTRL_STAT_SPEED_10M (0x0)
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#define MIIM_AUX_CNTRL_STAT_SPEED_100M (0x1)
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#define MIIM_AUX_CNTRL_STAT_SPEED_1000M (0x2)
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/* Std Page Register 23 - Extended PHY CTRL_1 */
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#define MSCC_PHY_EXT_PHY_CNTL_1_REG 23
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#define MAC_IF_SELECTION_MASK (0x1800)
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#define MAC_IF_SELECTION_GMII (0)
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#define MAC_IF_SELECTION_RMII (1)
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#define MAC_IF_SELECTION_RGMII (2)
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#define MAC_IF_SELECTION_POS (11)
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#define MAC_IF_SELECTION_WIDTH (2)
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/* Extended Page 2 Register 20E2 */
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#define MSCC_PHY_RGMII_CNTL_REG 20
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#define VSC_FAST_LINK_FAIL2_ENA_MASK (0x8000)
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#define RX_CLK_OUT_MASK (0x0800)
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#define RX_CLK_OUT_POS (11)
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#define RX_CLK_OUT_WIDTH (1)
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#define RX_CLK_OUT_NORMAL (0)
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#define RX_CLK_OUT_DISABLE (1)
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#define RGMII_RX_CLK_DELAY_POS (4)
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#define RGMII_RX_CLK_DELAY_WIDTH (3)
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#define RGMII_RX_CLK_DELAY_MASK (0x0070)
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#define RGMII_TX_CLK_DELAY_POS (0)
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#define RGMII_TX_CLK_DELAY_WIDTH (3)
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#define RGMII_TX_CLK_DELAY_MASK (0x0007)
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/* Extended Page 2 Register 27E2 */
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#define MSCC_PHY_WOL_MAC_CONTROL 27
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#define EDGE_RATE_CNTL_POS (5)
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#define EDGE_RATE_CNTL_WIDTH (3)
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#define EDGE_RATE_CNTL_MASK (0x00E0)
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#define RMII_CLK_OUT_ENABLE_POS (4)
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#define RMII_CLK_OUT_ENABLE_WIDTH (1)
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#define RMII_CLK_OUT_ENABLE_MASK (0x10)
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/* Token Ring Page 0x52B5 Registers */
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#define MSCC_PHY_REG_TR_ADDR_16 16
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#define MSCC_PHY_REG_TR_DATA_17 17
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#define MSCC_PHY_REG_TR_DATA_18 18
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/* Token Ring - Read Value in */
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#define MSCC_PHY_TR_16_READ (0xA000)
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/* Token Ring - Write Value out */
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#define MSCC_PHY_TR_16_WRITE (0x8000)
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/* Token Ring Registers */
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#define MSCC_PHY_TR_LINKDETCTRL_POS (3)
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#define MSCC_PHY_TR_LINKDETCTRL_WIDTH (2)
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#define MSCC_PHY_TR_LINKDETCTRL_VAL (3)
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#define MSCC_PHY_TR_LINKDETCTRL_MASK (0x0018)
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#define MSCC_PHY_TR_LINKDETCTRL_ADDR (0x07F8)
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#define MSCC_PHY_TR_VGATHRESH100_POS (0)
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#define MSCC_PHY_TR_VGATHRESH100_WIDTH (7)
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#define MSCC_PHY_TR_VGATHRESH100_VAL (0x0018)
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#define MSCC_PHY_TR_VGATHRESH100_MASK (0x007f)
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#define MSCC_PHY_TR_VGATHRESH100_ADDR (0x0FA4)
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#define MSCC_PHY_TR_VGAGAIN10_U_POS (0)
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#define MSCC_PHY_TR_VGAGAIN10_U_WIDTH (1)
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#define MSCC_PHY_TR_VGAGAIN10_U_MASK (0x0001)
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#define MSCC_PHY_TR_VGAGAIN10_U_VAL (0)
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#define MSCC_PHY_TR_VGAGAIN10_L_POS (12)
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#define MSCC_PHY_TR_VGAGAIN10_L_WIDTH (4)
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#define MSCC_PHY_TR_VGAGAIN10_L_MASK (0xf000)
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#define MSCC_PHY_TR_VGAGAIN10_L_VAL (0x0001)
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#define MSCC_PHY_TR_VGAGAIN10_ADDR (0x0F92)
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/* General Timeout Values */
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#define MSCC_PHY_RESET_TIMEOUT (100)
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#define MSCC_PHY_MICRO_TIMEOUT (500)
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/* RGMII/GMII Clock Delay (Skew) Options */ enum vsc_phy_rgmii_skew {
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VSC_PHY_RGMII_DELAY_200_PS,
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VSC_PHY_RGMII_DELAY_800_PS,
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VSC_PHY_RGMII_DELAY_1100_PS,
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VSC_PHY_RGMII_DELAY_1700_PS,
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VSC_PHY_RGMII_DELAY_2000_PS,
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VSC_PHY_RGMII_DELAY_2300_PS,
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VSC_PHY_RGMII_DELAY_2600_PS,
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VSC_PHY_RGMII_DELAY_3400_PS,
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};
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/* MAC i/f Clock Edge Rage Control (Slew), See Reg27E2 */ enum
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vsc_phy_clk_slew {
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VSC_PHY_CLK_SLEW_RATE_0,
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VSC_PHY_CLK_SLEW_RATE_1,
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VSC_PHY_CLK_SLEW_RATE_2,
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VSC_PHY_CLK_SLEW_RATE_3,
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VSC_PHY_CLK_SLEW_RATE_4,
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VSC_PHY_CLK_SLEW_RATE_5,
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VSC_PHY_CLK_SLEW_RATE_6,
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VSC_PHY_CLK_SLEW_RATE_7,
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};
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static int mscc_vsc8531_vsc8541_init_scripts(struct phy_device *phydev)
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{
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u16 reg_val;
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/* Set to Access Token Ring Registers */
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phy_write(phydev, MDIO_DEVAD_NONE,
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MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
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/* Update LinkDetectCtrl default to optimized values */
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/* Determined during Silicon Validation Testing */
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16,
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(MSCC_PHY_TR_LINKDETCTRL_ADDR | MSCC_PHY_TR_16_READ));
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17);
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reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_LINKDETCTRL_POS,
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MSCC_PHY_TR_LINKDETCTRL_WIDTH,
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MSCC_PHY_TR_LINKDETCTRL_VAL);
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val);
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16,
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(MSCC_PHY_TR_LINKDETCTRL_ADDR | MSCC_PHY_TR_16_WRITE));
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/* Update VgaThresh100 defaults to optimized values */
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/* Determined during Silicon Validation Testing */
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16,
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(MSCC_PHY_TR_VGATHRESH100_ADDR | MSCC_PHY_TR_16_READ));
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18);
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reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGATHRESH100_POS,
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MSCC_PHY_TR_VGATHRESH100_WIDTH,
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MSCC_PHY_TR_VGATHRESH100_VAL);
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val);
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16,
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(MSCC_PHY_TR_VGATHRESH100_ADDR | MSCC_PHY_TR_16_WRITE));
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/* Update VgaGain10 defaults to optimized values */
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/* Determined during Silicon Validation Testing */
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16,
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(MSCC_PHY_TR_VGAGAIN10_ADDR | MSCC_PHY_TR_16_READ));
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18);
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reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_U_POS,
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MSCC_PHY_TR_VGAGAIN10_U_WIDTH,
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MSCC_PHY_TR_VGAGAIN10_U_VAL);
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val);
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17);
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reg_val = bitfield_replace(reg_val, MSCC_PHY_TR_VGAGAIN10_L_POS,
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MSCC_PHY_TR_VGAGAIN10_L_WIDTH,
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MSCC_PHY_TR_VGAGAIN10_L_VAL);
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val);
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16,
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(MSCC_PHY_TR_VGAGAIN10_ADDR | MSCC_PHY_TR_16_WRITE));
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/* Set back to Access Standard Page Registers */
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
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MSCC_PHY_PAGE_STD);
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return 0;
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}
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static int mscc_parse_status(struct phy_device *phydev)
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{
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u16 speed;
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u16 mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_AUX_CNTRL_STAT_REG);
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if (mii_reg & MIIM_AUX_CNTRL_STAT_F_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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speed = mii_reg & MIIM_AUX_CNTRL_STAT_SPEED_MASK;
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speed = speed >> MIIM_AUX_CNTRL_STAT_SPEED_POS;
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switch (speed) {
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case MIIM_AUX_CNTRL_STAT_SPEED_1000M:
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phydev->speed = SPEED_1000;
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break;
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case MIIM_AUX_CNTRL_STAT_SPEED_100M:
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phydev->speed = SPEED_100;
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break;
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case MIIM_AUX_CNTRL_STAT_SPEED_10M:
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phydev->speed = SPEED_10;
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break;
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default:
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phydev->speed = SPEED_10;
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break;
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}
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return 0;
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}
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static int mscc_startup(struct phy_device *phydev)
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{
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int retval;
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retval = genphy_update_link(phydev);
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if (retval)
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return retval;
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return mscc_parse_status(phydev);
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}
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static int mscc_phy_soft_reset(struct phy_device *phydev)
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{
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int retval = 0;
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u16 timeout = MSCC_PHY_RESET_TIMEOUT;
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u16 reg_val = 0;
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
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MSCC_PHY_PAGE_STD);
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (reg_val | BMCR_RESET));
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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while ((reg_val & BMCR_RESET) && (timeout > 0)) {
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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timeout--;
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udelay(1000); /* 1 ms */
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}
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if (timeout == 0) {
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printf("MSCC PHY Soft_Reset Error: mac i/f = 0x%x\n",
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phydev->interface);
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retval = -ETIME;
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}
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return retval;
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}
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static int vsc8531_vsc8541_mac_config(struct phy_device *phydev)
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{
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u16 reg_val = 0;
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u16 mac_if = 0;
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u16 rx_clk_out = 0;
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/* For VSC8530/31 the only MAC modes are RMII/RGMII. */
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/* For VSC8540/41 the only MAC modes are (G)MII and RMII/RGMII. */
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/* Setup MAC Configuration */
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_GMII:
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/* Set Reg23.12:11=0 */
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mac_if = MAC_IF_SELECTION_GMII;
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/* Set Reg20E2.11=1 */
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rx_clk_out = RX_CLK_OUT_DISABLE;
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* Set Reg23.12:11=1 */
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mac_if = MAC_IF_SELECTION_RMII;
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/* Set Reg20E2.11=0 */
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rx_clk_out = RX_CLK_OUT_NORMAL;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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/* Set Reg23.12:11=2 */
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mac_if = MAC_IF_SELECTION_RGMII;
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/* Set Reg20E2.11=0 */
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rx_clk_out = RX_CLK_OUT_NORMAL;
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break;
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default:
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printf("MSCC PHY - INVALID MAC i/f Config: mac i/f = 0x%x\n",
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phydev->interface);
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return -EINVAL;
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}
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
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MSCC_PHY_PAGE_STD);
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE,
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MSCC_PHY_EXT_PHY_CNTL_1_REG);
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/* Set MAC i/f bits Reg23.12:11 */
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reg_val = bitfield_replace(reg_val, MAC_IF_SELECTION_POS,
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MAC_IF_SELECTION_WIDTH, mac_if);
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/* Update Reg23.12:11 */
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phy_write(phydev, MDIO_DEVAD_NONE,
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MSCC_PHY_EXT_PHY_CNTL_1_REG, reg_val);
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/* Setup ExtPg_2 Register Access */
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phy_write(phydev, MDIO_DEVAD_NONE,
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MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXT2);
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/* Read Reg20E2 */
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE,
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MSCC_PHY_RGMII_CNTL_REG);
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reg_val = bitfield_replace(reg_val, RX_CLK_OUT_POS,
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RX_CLK_OUT_WIDTH, rx_clk_out);
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/* Update Reg20E2.11 */
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phy_write(phydev, MDIO_DEVAD_NONE,
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MSCC_PHY_RGMII_CNTL_REG, reg_val);
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/* Before leaving - Change back to Std Page Register Access */
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
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MSCC_PHY_PAGE_STD);
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return 0;
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}
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static int vsc8531_config(struct phy_device *phydev)
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{
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int retval = -EINVAL;
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u16 reg_val;
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u16 rmii_clk_out;
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enum vsc_phy_rgmii_skew rx_clk_skew = VSC_PHY_RGMII_DELAY_1700_PS;
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enum vsc_phy_rgmii_skew tx_clk_skew = VSC_PHY_RGMII_DELAY_800_PS;
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enum vsc_phy_clk_slew edge_rate = VSC_PHY_CLK_SLEW_RATE_4;
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/* For VSC8530/31 and VSC8540/41 the init scripts are the same */
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mscc_vsc8531_vsc8541_init_scripts(phydev);
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/* For VSC8530/31 the only MAC modes are RMII/RGMII. */
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RMII:
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case PHY_INTERFACE_MODE_RGMII:
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retval = vsc8531_vsc8541_mac_config(phydev);
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if (retval != 0)
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return retval;
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retval = mscc_phy_soft_reset(phydev);
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if (retval != 0)
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return retval;
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break;
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default:
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printf("PHY 8530/31 MAC i/f Config Error: mac i/f = 0x%x\n",
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phydev->interface);
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return -EINVAL;
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}
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/* Default RMII Clk Output to 0=OFF/1=ON */
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rmii_clk_out = 0;
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
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MSCC_PHY_PAGE_EXT2);
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);
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/* Reg20E2 - Update RGMII RX_Clk Skews. */
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reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,
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RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew);
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/* Reg20E2 - Update RGMII TX_Clk Skews. */
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reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,
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RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew);
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL);
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/* Reg27E2 - Update Clk Slew Rate. */
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reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS,
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EDGE_RATE_CNTL_WIDTH, edge_rate);
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/* Reg27E2 - Update RMII Clk Out. */
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reg_val = bitfield_replace(reg_val, RMII_CLK_OUT_ENABLE_POS,
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RMII_CLK_OUT_ENABLE_WIDTH, rmii_clk_out);
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/* Update Reg27E2 */
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
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phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
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MSCC_PHY_PAGE_STD);
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return genphy_config_aneg(phydev);
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}
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static int vsc8541_config(struct phy_device *phydev)
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{
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int retval = -EINVAL;
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u16 reg_val;
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|
u16 rmii_clk_out;
|
|
enum vsc_phy_rgmii_skew rx_clk_skew = VSC_PHY_RGMII_DELAY_1700_PS;
|
|
enum vsc_phy_rgmii_skew tx_clk_skew = VSC_PHY_RGMII_DELAY_800_PS;
|
|
enum vsc_phy_clk_slew edge_rate = VSC_PHY_CLK_SLEW_RATE_4;
|
|
|
|
/* For VSC8530/31 and VSC8540/41 the init scripts are the same */
|
|
mscc_vsc8531_vsc8541_init_scripts(phydev);
|
|
|
|
/* For VSC8540/41 the only MAC modes are (G)MII and RMII/RGMII. */
|
|
switch (phydev->interface) {
|
|
case PHY_INTERFACE_MODE_MII:
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
retval = vsc8531_vsc8541_mac_config(phydev);
|
|
if (retval != 0)
|
|
return retval;
|
|
|
|
retval = mscc_phy_soft_reset(phydev);
|
|
if (retval != 0)
|
|
return retval;
|
|
break;
|
|
default:
|
|
printf("PHY 8541 MAC i/f config Error: mac i/f = 0x%x\n",
|
|
phydev->interface);
|
|
return -EINVAL;
|
|
}
|
|
/* Default RMII Clk Output to 0=OFF/1=ON */
|
|
rmii_clk_out = 0;
|
|
|
|
phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
|
|
MSCC_PHY_PAGE_EXT2);
|
|
reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);
|
|
/* Reg20E2 - Update RGMII RX_Clk Skews. */
|
|
reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,
|
|
RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew);
|
|
/* Reg20E2 - Update RGMII TX_Clk Skews. */
|
|
reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,
|
|
RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew);
|
|
phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);
|
|
|
|
reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL);
|
|
/* Reg27E2 - Update Clk Slew Rate. */
|
|
reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS,
|
|
EDGE_RATE_CNTL_WIDTH, edge_rate);
|
|
/* Reg27E2 - Update RMII Clk Out. */
|
|
reg_val = bitfield_replace(reg_val, RMII_CLK_OUT_ENABLE_POS,
|
|
RMII_CLK_OUT_ENABLE_WIDTH, rmii_clk_out);
|
|
/* Update Reg27E2 */
|
|
phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
|
|
phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
|
|
MSCC_PHY_PAGE_STD);
|
|
|
|
return genphy_config_aneg(phydev);
|
|
}
|
|
|
|
static struct phy_driver VSC8530_driver = {
|
|
.name = "Microsemi VSC8530",
|
|
.uid = PHY_ID_VSC8530,
|
|
.mask = 0x000ffff0,
|
|
.features = PHY_BASIC_FEATURES,
|
|
.config = &vsc8531_config,
|
|
.startup = &mscc_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver VSC8531_driver = {
|
|
.name = "Microsemi VSC8531",
|
|
.uid = PHY_ID_VSC8531,
|
|
.mask = 0x000ffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &vsc8531_config,
|
|
.startup = &mscc_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver VSC8540_driver = {
|
|
.name = "Microsemi VSC8540",
|
|
.uid = PHY_ID_VSC8540,
|
|
.mask = 0x000ffff0,
|
|
.features = PHY_BASIC_FEATURES,
|
|
.config = &vsc8541_config,
|
|
.startup = &mscc_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver VSC8541_driver = {
|
|
.name = "Microsemi VSC8541",
|
|
.uid = PHY_ID_VSC8541,
|
|
.mask = 0x000ffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &vsc8541_config,
|
|
.startup = &mscc_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
int phy_mscc_init(void)
|
|
{
|
|
phy_register(&VSC8530_driver);
|
|
phy_register(&VSC8531_driver);
|
|
phy_register(&VSC8540_driver);
|
|
phy_register(&VSC8541_driver);
|
|
|
|
return 0;
|
|
}
|