mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 12:45:42 +00:00
84c5dd16a4
We need this way for SPL boot. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
155 lines
3.5 KiB
INI
155 lines
3.5 KiB
INI
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Jason Liu <r64343@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x020e05a8 0x00000030
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DATA 4 0x020e05b0 0x00000030
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DATA 4 0x020e0524 0x00000030
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DATA 4 0x020e051c 0x00000030
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DATA 4 0x020e0518 0x00000030
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DATA 4 0x020e050c 0x00000030
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DATA 4 0x020e05b8 0x00000030
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DATA 4 0x020e05c0 0x00000030
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DATA 4 0x020e05ac 0x00020030
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DATA 4 0x020e05b4 0x00020030
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DATA 4 0x020e0528 0x00020030
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DATA 4 0x020e0520 0x00020030
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DATA 4 0x020e0514 0x00020030
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DATA 4 0x020e0510 0x00020030
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DATA 4 0x020e05bc 0x00020030
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DATA 4 0x020e05c4 0x00020030
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DATA 4 0x020e056c 0x00020030
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DATA 4 0x020e0578 0x00020030
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DATA 4 0x020e0588 0x00020030
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DATA 4 0x020e0594 0x00020030
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DATA 4 0x020e057c 0x00020030
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DATA 4 0x020e0590 0x00003000
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DATA 4 0x020e0598 0x00003000
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DATA 4 0x020e058c 0x00000000
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DATA 4 0x020e059c 0x00003030
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DATA 4 0x020e05a0 0x00003030
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DATA 4 0x020e0784 0x00000030
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DATA 4 0x020e0788 0x00000030
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DATA 4 0x020e0794 0x00000030
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DATA 4 0x020e079c 0x00000030
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DATA 4 0x020e07a0 0x00000030
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DATA 4 0x020e07a4 0x00000030
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DATA 4 0x020e07a8 0x00000030
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DATA 4 0x020e0748 0x00000030
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DATA 4 0x020e074c 0x00000030
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DATA 4 0x020e0750 0x00020000
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DATA 4 0x020e0758 0x00000000
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DATA 4 0x020e0774 0x00020000
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DATA 4 0x020e078c 0x00000030
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DATA 4 0x020e0798 0x000C0000
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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DATA 4 0x021b481c 0x33333333
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DATA 4 0x021b4820 0x33333333
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DATA 4 0x021b4824 0x33333333
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DATA 4 0x021b4828 0x33333333
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DATA 4 0x021b0018 0x00081740
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b000c 0x555A7974
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DATA 4 0x021b0010 0xDB538F64
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DATA 4 0x021b0014 0x01FF00DB
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DATA 4 0x021b002c 0x000026D2
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DATA 4 0x021b0030 0x005A1023
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DATA 4 0x021b0008 0x09444040
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DATA 4 0x021b0004 0x00025576
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DATA 4 0x021b0040 0x00000027
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DATA 4 0x021b0000 0x831A0000
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DATA 4 0x021b001c 0x04088032
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DATA 4 0x021b001c 0x0408803A
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DATA 4 0x021b001c 0x00008033
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DATA 4 0x021b001c 0x0000803B
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DATA 4 0x021b001c 0x00428031
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DATA 4 0x021b001c 0x00428039
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DATA 4 0x021b001c 0x19308030
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DATA 4 0x021b001c 0x19308038
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DATA 4 0x021b001c 0x04008040
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DATA 4 0x021b001c 0x04008048
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DATA 4 0x021b0800 0xA1380003
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DATA 4 0x021b4800 0xA1380003
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DATA 4 0x021b0020 0x00005800
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DATA 4 0x021b0818 0x00022227
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DATA 4 0x021b4818 0x00022227
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DATA 4 0x021b083c 0x434B0350
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DATA 4 0x021b0840 0x034C0359
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DATA 4 0x021b483c 0x434B0350
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DATA 4 0x021b4840 0x03650348
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DATA 4 0x021b0848 0x4436383B
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DATA 4 0x021b4848 0x39393341
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DATA 4 0x021b0850 0x35373933
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DATA 4 0x021b4850 0x48254A36
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DATA 4 0x021b080c 0x001F001F
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DATA 4 0x021b0810 0x001F001F
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DATA 4 0x021b480c 0x00440044
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DATA 4 0x021b4810 0x00440044
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b48b8 0x00000800
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DATA 4 0x021b001c 0x00000000
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DATA 4 0x021b0404 0x00011006
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/*
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* Setup CCM_CCOSR register as follows:
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*
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* cko1_en = 1 --> CKO1 enabled
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* cko1_div = 111 --> divide by 8
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* cko1_sel = 1011 --> ahb_clk_root
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*
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* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
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*/
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DATA 4 0x020c4060 0x000000fb
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