mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 22:33:18 +00:00
46668df5d0
Memory dt node update introduced by spl_fixup_fdt() in below
commit was making DDR configuration in-appropriate
to boot falcon mode. Hence added dram_init_banksize for
explicit assignment of proper base and size of DDR.
"boot: fdt: Perform arch_fixup_fdt() on the given device tree for falcon boot"
(sha1: 6e7585bb64)
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
/*
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* Copyright (C) 2014 Gateworks Corporation
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* Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
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*
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* Author: Tim Harvey <tharvey@gateworks.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/spl.h>
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#include <spl.h>
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#include <asm/mach-imx/hab.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_MX6)
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/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
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u32 spl_boot_device(void)
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{
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unsigned int bmode = readl(&src_base->sbmr2);
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u32 reg = imx6_src_get_boot_mode();
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/*
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* Check for BMODE if serial downloader is enabled
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* BOOT_MODE - see IMX6DQRM Table 8-1
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*/
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if (((bmode >> 24) & 0x03) == 0x01) /* Serial Downloader */
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return BOOT_DEVICE_BOARD;
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/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
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switch ((reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
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/* EIM: See 8.5.1, Table 8-9 */
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case IMX6_BMODE_EMI:
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/* BOOT_CFG1[3]: NOR/OneNAND Selection */
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switch ((reg & IMX6_BMODE_EMI_MASK) >> IMX6_BMODE_EMI_SHIFT) {
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case IMX6_BMODE_ONENAND:
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return BOOT_DEVICE_ONENAND;
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case IMX6_BMODE_NOR:
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return BOOT_DEVICE_NOR;
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break;
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}
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/* Reserved: Used to force Serial Downloader */
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case IMX6_BMODE_RESERVED:
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return BOOT_DEVICE_BOARD;
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/* SATA: See 8.5.4, Table 8-20 */
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#if !defined(CONFIG_MX6UL) && !defined(CONFIG_MX6ULL)
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case IMX6_BMODE_SATA:
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return BOOT_DEVICE_SATA;
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#endif
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/* Serial ROM: See 8.5.5.1, Table 8-22 */
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case IMX6_BMODE_SERIAL_ROM:
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/* BOOT_CFG4[2:0] */
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switch ((reg & IMX6_BMODE_SERIAL_ROM_MASK) >>
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IMX6_BMODE_SERIAL_ROM_SHIFT) {
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case IMX6_BMODE_ECSPI1:
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case IMX6_BMODE_ECSPI2:
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case IMX6_BMODE_ECSPI3:
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case IMX6_BMODE_ECSPI4:
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case IMX6_BMODE_ECSPI5:
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return BOOT_DEVICE_SPI;
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case IMX6_BMODE_I2C1:
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case IMX6_BMODE_I2C2:
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case IMX6_BMODE_I2C3:
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return BOOT_DEVICE_I2C;
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}
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break;
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/* SD/eSD: 8.5.3, Table 8-15 */
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case IMX6_BMODE_SD:
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case IMX6_BMODE_ESD:
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return BOOT_DEVICE_MMC1;
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/* MMC/eMMC: 8.5.3 */
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case IMX6_BMODE_MMC:
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case IMX6_BMODE_EMMC:
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return BOOT_DEVICE_MMC1;
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/* NAND Flash: 8.5.2, Table 8-10 */
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case IMX6_BMODE_NAND:
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return BOOT_DEVICE_NAND;
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}
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return BOOT_DEVICE_NONE;
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}
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#endif
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#if defined(CONFIG_SPL_MMC_SUPPORT)
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/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
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u32 spl_boot_mode(const u32 boot_device)
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{
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switch (spl_boot_device()) {
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/* for MMC return either RAW or FAT mode */
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case BOOT_DEVICE_MMC1:
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case BOOT_DEVICE_MMC2:
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#if defined(CONFIG_SPL_FAT_SUPPORT)
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return MMCSD_MODE_FS;
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#elif defined(CONFIG_SUPPORT_EMMC_BOOT)
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return MMCSD_MODE_EMMCBOOT;
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#else
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return MMCSD_MODE_RAW;
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#endif
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break;
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default:
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puts("spl: ERROR: unsupported device\n");
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hang();
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}
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}
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#endif
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#if defined(CONFIG_SECURE_BOOT)
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__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
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{
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typedef void __noreturn (*image_entry_noargs_t)(void);
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image_entry_noargs_t image_entry =
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(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
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debug("image entry point: 0x%lX\n", spl_image->entry_point);
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/* HAB looks for the CSF at the end of the authenticated data therefore,
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* we need to subtract the size of the CSF from the actual filesize */
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if (authenticate_image(spl_image->load_addr,
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spl_image->size - CONFIG_CSF_SIZE)) {
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image_entry();
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} else {
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puts("spl: ERROR: image authentication unsuccessful\n");
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hang();
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}
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}
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#endif
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#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = imx_ddr_size();
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return 0;
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}
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#endif
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