mirror of
https://github.com/AsahiLinux/u-boot
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b9d0f00a9d
This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng@outlook.com>
60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021
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* lixinde <lixinde@phytium.com.cn>
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* weichangzheng <weichangzheng@phytium.com.cn>
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*/
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#include <stdio.h>
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#include <string.h>
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#include <linux/arm-smccc.h>
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#include <init.h>
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#include "cpu.h"
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struct pcu_ctr {
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u32 base_config[3];
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u32 equalization[3];
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u8 rev[80];
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} __attribute((aligned(4)));
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struct pcu_config {
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u32 magic;
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u32 version;
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u32 size;
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u8 rev1[4];
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u32 independent_tree;
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u32 base_cfg;
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u8 rev2[16];
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struct pcu_ctr ctr_cfg[2];
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} __attribute((aligned(4)));
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struct pcu_config const peu_base_info = {
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.magic = PARAMETER_PCIE_MAGIC,
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.version = 0x2,
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.size = 0x100,
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.independent_tree = CFG_INDEPENDENT_TREE,
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.base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))),
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.ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
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.ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
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.ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
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.ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
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.ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
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.ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED),
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.ctr_cfg[0].equalization[0] = 0x7,
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.ctr_cfg[0].equalization[1] = 0x7,
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.ctr_cfg[0].equalization[2] = 0x7,
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.ctr_cfg[1].equalization[0] = 0x7,
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.ctr_cfg[1].equalization[1] = 0x7,
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.ctr_cfg[1].equalization[2] = 0x7,
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};
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void pcie_init(void)
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{
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u8 buffer[0x100];
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struct arm_smccc_res res;
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memcpy(buffer, &peu_base_info, sizeof(peu_base_info));
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arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res);
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if (res.a0 != 0)
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panic("PCIE init failed :0x%lx\n", res.a0);
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}
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