mirror of
https://github.com/AsahiLinux/u-boot
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a325e7e8bd
The serial clock is provided by the get_serial_clock() callback on PPC under DM_SERIAL. Use the same method to compute the clock as for non-DM_SERIAL use cases. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
183 lines
3.8 KiB
C
183 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2023 NXP
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*/
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#include <common.h>
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#include <command.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <image.h>
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#include <init.h>
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#include <netdev.h>
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#include <asm/global_data.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_liodn.h>
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#include <clock_legacy.h>
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#include <fm_eth.h>
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#include "t4rdb.h"
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#include "cpld.h"
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#include "../common/vid.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_IS_ENABLED(DM_SERIAL)
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int get_serial_clock(void)
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{
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return get_bus_freq(0) / 2;
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}
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#endif
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int checkboard(void)
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{
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struct cpu_type *cpu = gd->arch.cpu;
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u8 sw;
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printf("Board: %sRDB, ", cpu->name);
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printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
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CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
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sw = CPLD_READ(vbank);
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sw = sw & CPLD_BANK_SEL_MASK;
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if (sw <= 7)
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printf("vBank: %d\n", sw);
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else
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printf("Unsupported Bank=%x\n", sw);
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puts("SERDES Reference Clocks:\n");
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printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
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" SERDES3=100MHz SERDES4=100MHz\n");
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CFG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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/*
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* Adjust core voltage according to voltage ID
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* This function changes I2C mux to channel 2.
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*/
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if (adjust_vdd(0))
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printf("Warning: Adjusting core voltage failed.\n");
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pci_init();
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return 0;
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}
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int misc_init_r(void)
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{
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = env_get_bootm_low();
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size = env_get_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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fsl_fdt_fixup_dr_usb(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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#ifndef CONFIG_DM_ETH
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fdt_fixup_fman_ethernet(blob);
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#endif
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fdt_fixup_board_enet(blob);
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#endif
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return 0;
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}
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/*
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* This function is called by bdinfo to print detail board information.
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* As an exmaple for future board, we organize the messages into
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* several sections. If applicable, the message is in the format of
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* <name> = <value>
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* It should aligned with normal output of bdinfo command.
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*
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* Voltage: Core, DDR and another configurable voltages
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* Clock : Critical clocks which are not printed already
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* RCW : RCW source if not printed already
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* Misc : Other important information not in above catagories
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*/
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void board_detail(void)
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{
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int rcwsrc;
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/* RCW section SW3[4] */
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rcwsrc = 0x0;
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puts("RCW source = ");
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switch (rcwsrc & 0x1) {
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case 0x1:
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puts("SDHC/eMMC\n");
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break;
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default:
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puts("I2C normal addressing\n");
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break;
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}
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}
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ulong *cs4340_get_fw_addr(void)
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{
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ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
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#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
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u8 sw;
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sw = CPLD_READ(vbank);
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sw = sw & CPLD_BANK_SEL_MASK;
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if (sw == 0)
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cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
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else if (sw == 4)
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cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
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#endif
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return (ulong *)cortina_fw_addr;
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}
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