Dave Liu 6a81978367 fsl-ddr: Fix two bugs in the ddr infrastructure ... 1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case. Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com>		2009-03-30 13:33:50 -05:00
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ddr	fsl-ddr: Fix two bugs in the ddr infrastructure	2009-03-30 13:33:50 -05:00