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2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm-offsets.h>
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#include <clock_legacy.h>
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#include <mpc83xx.h>
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#include <time.h>
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#include <asm/global_data.h>
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#include "lblaw/lblaw.h"
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#include "elbc/elbc.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f (volatile immap_t * im)
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{
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/* global data region was cleared in start.S */
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/* system performance tweaking */
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#ifndef CONFIG_ACR_PIPE_DEP_UNSET
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/* Arbiter pipeline depth */
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im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
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CONFIG_ACR_PIPE_DEP;
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#endif
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#ifndef CONFIG_ACR_RPTCNT_UNSET
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/* Arbiter repeat count */
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im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
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CONFIG_ACR_RPTCNT;
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#endif
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#ifdef CONFIG_SYS_SPCR_OPT
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/* Optimize transactions between CSB and other devices */
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
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(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
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#endif
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/* Enable Time Base & Decrementer (so we will have udelay()) */
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im->sysconf.spcr |= SPCR_TBEN;
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/* DDR control driver register */
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#ifdef CONFIG_SYS_DDRCDR
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
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#endif
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/* Output buffer impedance register */
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#ifdef CONFIG_SYS_OBIR
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im->sysconf.obir = CONFIG_SYS_OBIR;
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#endif
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/*
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* Memory Controller:
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*/
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/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
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* addresses - these have to be modified later when FLASH size
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* has been determined
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*/
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#if defined(CONFIG_SYS_NAND_BR_PRELIM) \
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&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
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&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
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&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
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set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
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set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
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im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
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im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
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#else
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#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
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#endif
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}
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/*
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* Get timebase clock frequency (like cpu_clk in Hz)
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*/
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unsigned long get_tbclk(void)
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{
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return (gd->bus_clk + 3L) / 4L;
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}
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void puts(const char *str)
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{
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while (*str)
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putc(*str++);
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}
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ulong get_bus_freq(ulong dummy)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
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return get_board_sys_clk() * spmf;
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}
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