mirror of
https://github.com/AsahiLinux/u-boot
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9ef89ea9b0
Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
38 lines
788 B
C
38 lines
788 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 NXP
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*/
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#ifndef __ASM_ARCH_IMX8ULP_DDR_H
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#define __ASM_ARCH_IMX8ULP_DDR_H
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#include <asm/io.h>
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#include <asm/types.h>
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struct dram_cfg_param {
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unsigned int reg;
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unsigned int val;
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};
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struct dram_timing_info2 {
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/* ddr controller config */
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struct dram_cfg_param *ctl_cfg;
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unsigned int ctl_cfg_num;
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/* pi config */
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struct dram_cfg_param *pi_cfg;
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unsigned int pi_cfg_num;
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/* phy freq1 config */
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struct dram_cfg_param *phy_f1_cfg;
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unsigned int phy_f1_cfg_num;
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/* phy freq2 config */
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struct dram_cfg_param *phy_f2_cfg;
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unsigned int phy_f2_cfg_num;
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/* initialized drate table */
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unsigned int fsp_table[3];
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};
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extern struct dram_timing_info2 dram_timing;
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int ddr_init(struct dram_timing_info2 *dram_timing);
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#endif
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