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u-boot/drivers/clk/rockchip
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Kever Yang 6a464d9cab rockchip: clk: rk3036: correct setting for pll integer mode 
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-23 16:40:23 +02:00
..
clk_rk3036.c rockchip: clk: rk3036: correct setting for pll integer mode 2017-06-23 16:40:23 +02:00
clk_rk3188.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rk3288.c rockchip: Init clocks again when chain-loading 2017-06-09 13:45:33 -06:00
clk_rk3328.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rk3368.c rockchip: rk3368: Add clock driver 2017-06-07 07:29:19 -06:00
clk_rk3399.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rv1108.c rockchip: clk: Add rv1108 clock driver 2017-06-07 07:29:25 -06:00
Makefile rockchip: clk: Add rv1108 clock driver 2017-06-07 07:29:25 -06:00