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This patch updates the PLB/PCI divider when running at 400MHz CPU frequency from 4 to 3 which results in 44MHz PCI sync clock. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
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.. | ||
cmd_pmc440.c | ||
config.mk | ||
fpga.c | ||
fpga.h | ||
init.S | ||
Makefile | ||
pmc440.c | ||
pmc440.h | ||
sdram.c | ||
u-boot-nand.lds | ||
u-boot.lds |