mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
6a3e4274e4
The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
/*
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* Copyright (C) 2013-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
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{
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u32 tmp;
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/*
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* Set DPLL SSC parameters for DPLLCTRL3
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* [23] DIVN_TEST 0x1
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* [22:16] DIVN 0x50
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* [10] FREFSEL_TEST 0x1
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* [9:8] FREFSEL 0x2
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* [4] ICPD_TEST 0x1
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* [3:0] ICPD 0xb
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*/
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tmp = readl(SC_DPLLCTRL3);
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tmp &= ~0x00ff0717;
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tmp |= 0x00d0061b;
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writel(tmp, SC_DPLLCTRL3);
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/*
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* Set DPLL SSC parameters for DPLLCTRL
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* <-1%> <-2%>
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* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
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* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
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*/
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tmp = readl(SC_DPLLCTRL);
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tmp &= ~0x3ff07fff;
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#ifdef DPLL_SSC_RATE_1PER
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tmp |= 0x084018bf;
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#else
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tmp |= 0x084031a6;
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#endif
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writel(tmp, SC_DPLLCTRL);
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/*
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* Set DPLL SSC parameters for DPLLCTRL2
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* [31:29] SSC_STEP 0
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* [27] SSC_REG_REF 1
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* [26:20] SSC_M 79 (0x4f)
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* [19:0] SSC_K 964689 (0xeb851)
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*/
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tmp = readl(SC_DPLLCTRL2);
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tmp &= ~0xefffffff;
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tmp |= 0x0cfeb851;
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writel(tmp, SC_DPLLCTRL2);
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/* Wait 500 usec until dpll gets stable */
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udelay(500);
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return 0;
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}
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