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9d922450aa
This header includes things that are needed to make driver build. Adjust existing users to include that always, even if other dm/ includes are present Signed-off-by: Simon Glass <sjg@chromium.org>
248 lines
6.2 KiB
C
248 lines
6.2 KiB
C
/*
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* Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mapmem.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include "pinctrl-imx.h"
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DECLARE_GLOBAL_DATA_PTR;
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static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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struct imx_pinctrl_priv *priv = dev_get_priv(dev);
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struct imx_pinctrl_soc_info *info = priv->info;
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int node = dev_of_offset(config);
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const struct fdt_property *prop;
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u32 *pin_data;
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int npins, size, pin_size;
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int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
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u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
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int i, j = 0;
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dev_dbg(dev, "%s: %s\n", __func__, config->name);
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if (info->flags & SHARE_MUX_CONF_REG)
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pin_size = SHARE_FSL_PIN_SIZE;
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else
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pin_size = FSL_PIN_SIZE;
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prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
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if (!prop) {
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dev_err(dev, "No fsl,pins property in node %s\n", config->name);
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return -EINVAL;
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}
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if (!size || size % pin_size) {
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dev_err(dev, "Invalid fsl,pins property in node %s\n",
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config->name);
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return -EINVAL;
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}
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pin_data = devm_kzalloc(dev, size, 0);
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if (!pin_data)
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return -ENOMEM;
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if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
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pin_data, size >> 2)) {
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dev_err(dev, "Error reading pin data.\n");
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devm_kfree(dev, pin_data);
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return -EINVAL;
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}
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npins = size / pin_size;
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/*
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* Refer to linux documentation for details:
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* Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
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*/
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for (i = 0; i < npins; i++) {
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mux_reg = pin_data[j++];
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if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
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mux_reg = -1;
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if (info->flags & SHARE_MUX_CONF_REG) {
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conf_reg = mux_reg;
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} else {
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conf_reg = pin_data[j++];
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if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
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conf_reg = -1;
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}
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if ((mux_reg == -1) || (conf_reg == -1)) {
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dev_err(dev, "Error mux_reg or conf_reg\n");
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devm_kfree(dev, pin_data);
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return -EINVAL;
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}
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input_reg = pin_data[j++];
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mux_mode = pin_data[j++];
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input_val = pin_data[j++];
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config_val = pin_data[j++];
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dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
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"mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
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mux_reg, conf_reg, input_reg, mux_mode, input_val,
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config_val);
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if (config_val & IMX_PAD_SION)
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mux_mode |= IOMUXC_CONFIG_SION;
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config_val &= ~IMX_PAD_SION;
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/* Set Mux */
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if (info->flags & SHARE_MUX_CONF_REG) {
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clrsetbits_le32(info->base + mux_reg, info->mux_mask,
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mux_mode << mux_shift);
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} else {
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writel(mux_mode, info->base + mux_reg);
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}
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dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg,
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mux_mode);
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/*
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* Set select input
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*
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* If the select input value begins with 0xff, it's a quirky
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* select input and the value should be interpreted as below.
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* 31 23 15 7 0
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* | 0xff | shift | width | select |
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* It's used to work around the problem that the select
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* input for some pin is not implemented in the select
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* input register but in some general purpose register.
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* We encode the select input value, width and shift of
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* the bit field into input_val cell of pin function ID
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* in device tree, and then decode them here for setting
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* up the select input bits in general purpose register.
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*/
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if (input_val >> 24 == 0xff) {
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u32 val = input_val;
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u8 select = val & 0xff;
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u8 width = (val >> 8) & 0xff;
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u8 shift = (val >> 16) & 0xff;
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u32 mask = ((1 << width) - 1) << shift;
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/*
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* The input_reg[i] here is actually some IOMUXC general
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* purpose register, not regular select input register.
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*/
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val = readl(info->base + input_reg);
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val &= ~mask;
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val |= select << shift;
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writel(val, info->base + input_reg);
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} else if (input_reg) {
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/*
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* Regular select input register can never be at offset
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* 0, and we only print register value for regular case.
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*/
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if (info->input_sel_base)
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writel(input_val, info->input_sel_base +
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input_reg);
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else
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writel(input_val, info->base + input_reg);
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dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
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input_reg, input_val);
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}
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/* Set config */
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if (!(config_val & IMX_NO_PAD_CTL)) {
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if (info->flags & SHARE_MUX_CONF_REG) {
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clrsetbits_le32(info->base + conf_reg,
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info->mux_mask, config_val);
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} else {
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writel(config_val, info->base + conf_reg);
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}
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dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
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conf_reg, config_val);
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}
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}
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devm_kfree(dev, pin_data);
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return 0;
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}
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const struct pinctrl_ops imx_pinctrl_ops = {
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.set_state = imx_pinctrl_set_state,
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};
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int imx_pinctrl_probe(struct udevice *dev,
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struct imx_pinctrl_soc_info *info)
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{
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struct imx_pinctrl_priv *priv = dev_get_priv(dev);
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int node = dev_of_offset(dev), ret;
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struct fdtdec_phandle_args arg;
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fdt_addr_t addr;
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fdt_size_t size;
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if (!info) {
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dev_err(dev, "wrong pinctrl info\n");
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return -EINVAL;
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}
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priv->dev = dev;
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priv->info = info;
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addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
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&size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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info->base = map_sysmem(addr, size);
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if (!info->base)
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return -ENOMEM;
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priv->info = info;
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info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
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/*
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* Refer to linux documentation for details:
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* Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
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*/
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if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
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ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
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node, "fsl,input-sel",
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NULL, 0, 0, &arg);
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if (ret) {
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dev_err(dev, "iomuxc fsl,input-sel property not found\n");
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return -EINVAL;
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}
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addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
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&size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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info->input_sel_base = map_sysmem(addr, size);
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if (!info->input_sel_base)
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return -ENOMEM;
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}
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dev_dbg(dev, "initialized IMX pinctrl driver\n");
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return 0;
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}
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int imx_pinctrl_remove(struct udevice *dev)
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{
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struct imx_pinctrl_priv *priv = dev_get_priv(dev);
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struct imx_pinctrl_soc_info *info = priv->info;
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if (info->input_sel_base)
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unmap_sysmem(info->input_sel_base);
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if (info->base)
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unmap_sysmem(info->base);
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return 0;
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}
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