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ba5eb2327b
Import misc cvmx-helper header files from 2013 U-Boot. They will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
516 lines
13 KiB
C
516 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018-2022 Marvell International Ltd.
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*
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* Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
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* clause 22 and clause 45 operations.
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*/
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#ifndef __CVMX_MIO_H__
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#define __CVMX_MIO_H__
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/**
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* PHY register 0 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_CONTROL 0
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typedef union {
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u16 u16;
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struct {
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u16 reset : 1;
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u16 loopback : 1;
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u16 speed_lsb : 1;
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u16 autoneg_enable : 1;
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u16 power_down : 1;
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u16 isolate : 1;
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u16 restart_autoneg : 1;
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u16 duplex : 1;
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u16 collision_test : 1;
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u16 speed_msb : 1;
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u16 unidirectional_enable : 1;
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u16 reserved_0_4 : 5;
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} s;
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} cvmx_mdio_phy_reg_control_t;
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/**
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* PHY register 1 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_STATUS 1
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typedef union {
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u16 u16;
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struct {
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u16 capable_100base_t4 : 1;
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u16 capable_100base_x_full : 1;
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u16 capable_100base_x_half : 1;
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u16 capable_10_full : 1;
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u16 capable_10_half : 1;
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u16 capable_100base_t2_full : 1;
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u16 capable_100base_t2_half : 1;
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u16 capable_extended_status : 1;
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u16 capable_unidirectional : 1;
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u16 capable_mf_preamble_suppression : 1;
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u16 autoneg_complete : 1;
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u16 remote_fault : 1;
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u16 capable_autoneg : 1;
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u16 link_status : 1;
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u16 jabber_detect : 1;
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u16 capable_extended_registers : 1;
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} s;
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} cvmx_mdio_phy_reg_status_t;
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/**
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* PHY register 2 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_ID1 2
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typedef union {
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u16 u16;
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struct {
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u16 oui_bits_3_18;
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} s;
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} cvmx_mdio_phy_reg_id1_t;
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/**
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* PHY register 3 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_ID2 3
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typedef union {
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u16 u16;
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struct {
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u16 oui_bits_19_24 : 6;
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u16 model : 6;
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u16 revision : 4;
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} s;
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} cvmx_mdio_phy_reg_id2_t;
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/**
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* PHY register 4 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
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typedef union {
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u16 u16;
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struct {
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u16 next_page : 1;
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u16 reserved_14 : 1;
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u16 remote_fault : 1;
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u16 reserved_12 : 1;
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u16 asymmetric_pause : 1;
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u16 pause : 1;
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u16 advert_100base_t4 : 1;
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u16 advert_100base_tx_full : 1;
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u16 advert_100base_tx_half : 1;
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u16 advert_10base_tx_full : 1;
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u16 advert_10base_tx_half : 1;
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u16 selector : 5;
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} s;
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} cvmx_mdio_phy_reg_autoneg_adver_t;
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/**
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* PHY register 5 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
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typedef union {
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u16 u16;
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struct {
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u16 next_page : 1;
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u16 ack : 1;
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u16 remote_fault : 1;
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u16 reserved_12 : 1;
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u16 asymmetric_pause : 1;
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u16 pause : 1;
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u16 advert_100base_t4 : 1;
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u16 advert_100base_tx_full : 1;
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u16 advert_100base_tx_half : 1;
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u16 advert_10base_tx_full : 1;
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u16 advert_10base_tx_half : 1;
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u16 selector : 5;
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} s;
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} cvmx_mdio_phy_reg_link_partner_ability_t;
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/**
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* PHY register 6 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
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typedef union {
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u16 u16;
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struct {
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u16 reserved_5_15 : 11;
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u16 parallel_detection_fault : 1;
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u16 link_partner_next_page_capable : 1;
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u16 local_next_page_capable : 1;
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u16 page_received : 1;
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u16 link_partner_autoneg_capable : 1;
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} s;
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} cvmx_mdio_phy_reg_autoneg_expansion_t;
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/**
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* PHY register 9 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
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typedef union {
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u16 u16;
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struct {
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u16 test_mode : 3;
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u16 manual_master_slave : 1;
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u16 master : 1;
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u16 port_type : 1;
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u16 advert_1000base_t_full : 1;
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u16 advert_1000base_t_half : 1;
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u16 reserved_0_7 : 8;
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} s;
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} cvmx_mdio_phy_reg_control_1000_t;
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/**
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* PHY register 10 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_STATUS_1000 10
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typedef union {
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u16 u16;
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struct {
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u16 master_slave_fault : 1;
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u16 is_master : 1;
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u16 local_receiver_ok : 1;
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u16 remote_receiver_ok : 1;
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u16 remote_capable_1000base_t_full : 1;
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u16 remote_capable_1000base_t_half : 1;
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u16 reserved_8_9 : 2;
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u16 idle_error_count : 8;
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} s;
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} cvmx_mdio_phy_reg_status_1000_t;
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/**
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* PHY register 15 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
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typedef union {
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u16 u16;
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struct {
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u16 capable_1000base_x_full : 1;
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u16 capable_1000base_x_half : 1;
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u16 capable_1000base_t_full : 1;
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u16 capable_1000base_t_half : 1;
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u16 reserved_0_11 : 12;
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} s;
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} cvmx_mdio_phy_reg_extended_status_t;
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/**
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* PHY register 13 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
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typedef union {
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u16 u16;
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struct {
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u16 function : 2;
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u16 reserved_5_13 : 9;
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u16 devad : 5;
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} s;
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} cvmx_mdio_phy_reg_mmd_control_t;
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/**
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* PHY register 14 from the 802.3 spec
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*/
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#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
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typedef union {
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u16 u16;
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struct {
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u16 address_data : 16;
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} s;
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} cvmx_mdio_phy_reg_mmd_address_data_t;
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/* Operating request encodings. */
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#define MDIO_CLAUSE_22_WRITE 0
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#define MDIO_CLAUSE_22_READ 1
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#define MDIO_CLAUSE_45_ADDRESS 0
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#define MDIO_CLAUSE_45_WRITE 1
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#define MDIO_CLAUSE_45_READ_INC 2
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#define MDIO_CLAUSE_45_READ 3
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/* MMD identifiers, mostly for accessing devices within XENPAK modules. */
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#define CVMX_MMD_DEVICE_PMA_PMD 1
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#define CVMX_MMD_DEVICE_WIS 2
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#define CVMX_MMD_DEVICE_PCS 3
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#define CVMX_MMD_DEVICE_PHY_XS 4
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#define CVMX_MMD_DEVICE_DTS_XS 5
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#define CVMX_MMD_DEVICE_TC 6
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#define CVMX_MMD_DEVICE_CL22_EXT 29
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#define CVMX_MMD_DEVICE_VENDOR_1 30
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#define CVMX_MMD_DEVICE_VENDOR_2 31
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#define CVMX_MDIO_TIMEOUT 100000 /* 100 millisec */
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static inline int cvmx_mdio_bus_id_to_node(int bus_id)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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return (bus_id >> 2) & CVMX_NODE_MASK;
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else
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return 0;
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}
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static inline int cvmx_mdio_bus_id_to_bus(int bus_id)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN78XX))
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return bus_id & 3;
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else
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return bus_id;
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}
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/* Helper function to put MDIO interface into clause 45 mode */
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static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
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{
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cvmx_smix_clk_t smi_clk;
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int node = cvmx_mdio_bus_id_to_node(bus_id);
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int bus = cvmx_mdio_bus_id_to_bus(bus_id);
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/* Put bus into clause 45 mode */
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smi_clk.u64 = csr_rd_node(node, CVMX_SMIX_CLK(bus));
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smi_clk.s.mode = 1;
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smi_clk.s.preamble = 1;
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csr_wr_node(node, CVMX_SMIX_CLK(bus), smi_clk.u64);
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}
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/* Helper function to put MDIO interface into clause 22 mode */
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static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
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{
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cvmx_smix_clk_t smi_clk;
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int node = cvmx_mdio_bus_id_to_node(bus_id);
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int bus = cvmx_mdio_bus_id_to_bus(bus_id);
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/* Put bus into clause 22 mode */
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smi_clk.u64 = csr_rd_node(node, CVMX_SMIX_CLK(bus));
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smi_clk.s.mode = 0;
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csr_wr_node(node, CVMX_SMIX_CLK(bus), smi_clk.u64);
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}
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/**
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* @INTERNAL
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* Function to read SMIX_RD_DAT and check for timeouts. This
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* code sequence is done fairly often, so put in one spot.
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*
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* @param bus_id SMI/MDIO bus to read
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*
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* @return Value of SMIX_RD_DAT. pending will be set on
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* a timeout.
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*/
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static inline cvmx_smix_rd_dat_t __cvmx_mdio_read_rd_dat(int bus_id)
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{
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cvmx_smix_rd_dat_t smi_rd;
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int node = cvmx_mdio_bus_id_to_node(bus_id);
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int bus = cvmx_mdio_bus_id_to_bus(bus_id);
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u64 done;
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done = get_timer(0);
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do {
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mdelay(1);
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smi_rd.u64 = csr_rd_node(node, CVMX_SMIX_RD_DAT(bus));
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if (get_timer(done) > (CVMX_MDIO_TIMEOUT / 1000))
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break;
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} while (smi_rd.s.pending);
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return smi_rd;
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}
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/**
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* Perform an MII read. This function is used to read PHY
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* registers controlling auto negotiation.
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*
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* @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
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* support multiple busses.
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* @param phy_id The MII phy id
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* @param location Register location to read
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*
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* @return Result from the read or -1 on failure
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*/
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static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
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{
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int node = cvmx_mdio_bus_id_to_node(bus_id);
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int bus = cvmx_mdio_bus_id_to_bus(bus_id);
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cvmx_smix_cmd_t smi_cmd;
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cvmx_smix_rd_dat_t smi_rd;
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if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
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__cvmx_mdio_set_clause22_mode(bus_id);
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = location;
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csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
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smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
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if (smi_rd.s.val)
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return smi_rd.s.dat;
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else
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return -1;
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}
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/**
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* Perform an MII write. This function is used to write PHY
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* registers controlling auto negotiation.
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*
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* @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
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* support multiple busses.
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* @param phy_id The MII phy id
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* @param location Register location to write
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* @param val Value to write
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*
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* @return -1 on error
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* 0 on success
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*/
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static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
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{
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int node = cvmx_mdio_bus_id_to_node(bus_id);
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int bus = cvmx_mdio_bus_id_to_bus(bus_id);
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cvmx_smix_cmd_t smi_cmd;
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cvmx_smix_wr_dat_t smi_wr;
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if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
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__cvmx_mdio_set_clause22_mode(bus_id);
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smi_wr.u64 = 0;
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smi_wr.s.dat = val;
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csr_wr_node(node, CVMX_SMIX_WR_DAT(bus), smi_wr.u64);
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = location;
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csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
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if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_SMIX_WR_DAT(bus),
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cvmx_smix_wr_dat_t, pending, ==, 0,
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CVMX_MDIO_TIMEOUT))
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return -1;
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return 0;
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}
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/**
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* Perform an IEEE 802.3 clause 45 MII read. This function is used to read PHY
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* registers controlling auto negotiation.
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*
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* @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
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* support multiple busses.
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* @param phy_id The MII phy id
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* @param device MDIO Manageable Device (MMD) id
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* @param location Register location to read
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*
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* @return Result from the read or -1 on failure
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*/
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static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
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int location)
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{
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cvmx_smix_cmd_t smi_cmd;
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cvmx_smix_rd_dat_t smi_rd;
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cvmx_smix_wr_dat_t smi_wr;
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int node = cvmx_mdio_bus_id_to_node(bus_id);
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int bus = cvmx_mdio_bus_id_to_bus(bus_id);
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if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
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return -1;
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__cvmx_mdio_set_clause45_mode(bus_id);
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smi_wr.u64 = 0;
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smi_wr.s.dat = location;
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csr_wr_node(node, CVMX_SMIX_WR_DAT(bus), smi_wr.u64);
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = device;
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csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
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if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_SMIX_WR_DAT(bus),
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cvmx_smix_wr_dat_t, pending, ==, 0,
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CVMX_MDIO_TIMEOUT)) {
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debug("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d TIME OUT(address)\n",
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bus_id, phy_id, device, location);
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return -1;
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}
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = device;
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csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
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smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
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if (smi_rd.s.pending) {
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debug("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d TIME OUT(data)\n",
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bus_id, phy_id, device, location);
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return -1;
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}
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if (smi_rd.s.val)
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return smi_rd.s.dat;
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debug("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d INVALID READ\n",
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bus_id, phy_id, device, location);
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return -1;
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}
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/**
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* Perform an IEEE 802.3 clause 45 MII write. This function is used to write PHY
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* registers controlling auto negotiation.
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*
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* @param bus_id MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
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* support multiple busses.
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* @param phy_id The MII phy id
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* @param device MDIO Manageable Device (MMD) id
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* @param location Register location to write
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* @param val Value to write
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*
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* @return -1 on error
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* 0 on success
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*/
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static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
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int location, int val)
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{
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cvmx_smix_cmd_t smi_cmd;
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cvmx_smix_wr_dat_t smi_wr;
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int node = cvmx_mdio_bus_id_to_node(bus_id);
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int bus = cvmx_mdio_bus_id_to_bus(bus_id);
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if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
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return -1;
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|
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__cvmx_mdio_set_clause45_mode(bus_id);
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|
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smi_wr.u64 = 0;
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smi_wr.s.dat = location;
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csr_wr_node(node, CVMX_SMIX_WR_DAT(bus), smi_wr.u64);
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = device;
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csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
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if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_SMIX_WR_DAT(bus),
|
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cvmx_smix_wr_dat_t, pending, ==, 0,
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|
CVMX_MDIO_TIMEOUT))
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return -1;
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|
|
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smi_wr.u64 = 0;
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smi_wr.s.dat = val;
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csr_wr_node(node, CVMX_SMIX_WR_DAT(bus), smi_wr.u64);
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|
|
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = device;
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csr_wr_node(node, CVMX_SMIX_CMD(bus), smi_cmd.u64);
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|
|
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if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_SMIX_WR_DAT(bus),
|
|
cvmx_smix_wr_dat_t, pending, ==, 0,
|
|
CVMX_MDIO_TIMEOUT))
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return -1;
|
|
|
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return 0;
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}
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#endif
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