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8ee802f899
For eMMC HS400 mode, the DLL reset is a required step for mmc rescan. This step has not been documented in reference manual, but the RM will be fixed sooner or later. In previous commit to support eMMC HS400,db8f936mmc: fsl_esdhc: support eMMC HS400 mode the steps to configure DLL could be found in commit message, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. these would be fixed as, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 13.1 Write DLLCFG0[DLL_RESET] to 1 and wait for 1us, then write DLLCFG0[DLL_RESET] 14. Wait for delay chain to lock. This patch is to add the step of DLL reset, and make sure delay chain locked for HS400. Fixes:db8f93672b("mmc: fsl_esdhc: support eMMC HS400 mode") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
256 lines
7.5 KiB
C
256 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* FSL SD/MMC Defines
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*-------------------------------------------------------------------
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*
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* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
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* Copyright 2020 NXP
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*/
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#ifndef __FSL_ESDHC_H__
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#define __FSL_ESDHC_H__
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#include <linux/errno.h>
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#include <asm/byteorder.h>
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/* needed for the mmc_cfg definition */
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#include <mmc.h>
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/* FSL eSDHC-specific constants */
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#define SYSCTL 0x0002e02c
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#define SYSCTL_INITA 0x08000000
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#define SYSCTL_TIMEOUT_MASK 0x000f0000
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#define SYSCTL_CLOCK_MASK 0x0000fff0
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#define SYSCTL_CKEN 0x00000008
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#define SYSCTL_PEREN 0x00000004
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#define SYSCTL_HCKEN 0x00000002
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#define SYSCTL_IPGEN 0x00000001
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#define SYSCTL_RSTA 0x01000000
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#define SYSCTL_RSTC 0x02000000
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#define SYSCTL_RSTD 0x04000000
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#define IRQSTAT 0x0002e030
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#define IRQSTAT_DMAE (0x10000000)
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#define IRQSTAT_AC12E (0x01000000)
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#define IRQSTAT_DEBE (0x00400000)
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#define IRQSTAT_DCE (0x00200000)
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#define IRQSTAT_DTOE (0x00100000)
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#define IRQSTAT_CIE (0x00080000)
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#define IRQSTAT_CEBE (0x00040000)
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#define IRQSTAT_CCE (0x00020000)
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#define IRQSTAT_CTOE (0x00010000)
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#define IRQSTAT_CINT (0x00000100)
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#define IRQSTAT_CRM (0x00000080)
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#define IRQSTAT_CINS (0x00000040)
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#define IRQSTAT_BRR (0x00000020)
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#define IRQSTAT_BWR (0x00000010)
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#define IRQSTAT_DINT (0x00000008)
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#define IRQSTAT_BGE (0x00000004)
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#define IRQSTAT_TC (0x00000002)
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#define IRQSTAT_CC (0x00000001)
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#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
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#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
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IRQSTAT_DMAE)
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#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
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#define IRQSTATEN 0x0002e034
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#define IRQSTATEN_DMAE (0x10000000)
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#define IRQSTATEN_AC12E (0x01000000)
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#define IRQSTATEN_DEBE (0x00400000)
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#define IRQSTATEN_DCE (0x00200000)
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#define IRQSTATEN_DTOE (0x00100000)
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#define IRQSTATEN_CIE (0x00080000)
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#define IRQSTATEN_CEBE (0x00040000)
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#define IRQSTATEN_CCE (0x00020000)
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#define IRQSTATEN_CTOE (0x00010000)
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#define IRQSTATEN_CINT (0x00000100)
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#define IRQSTATEN_CRM (0x00000080)
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#define IRQSTATEN_CINS (0x00000040)
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#define IRQSTATEN_BRR (0x00000020)
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#define IRQSTATEN_BWR (0x00000010)
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#define IRQSTATEN_DINT (0x00000008)
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#define IRQSTATEN_BGE (0x00000004)
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#define IRQSTATEN_TC (0x00000002)
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#define IRQSTATEN_CC (0x00000001)
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/* eSDHC control register */
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#define ESDHCCTL 0x0002e40c
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#define ESDHCCTL_PCS (0x00080000)
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#define ESDHCCTL_FAF (0x00040000)
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#define PRSSTAT 0x0002e024
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#define PRSSTAT_DAT0 (0x01000000)
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#define PRSSTAT_CLSL (0x00800000)
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#define PRSSTAT_WPSPL (0x00080000)
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#define PRSSTAT_CDPL (0x00040000)
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#define PRSSTAT_CINS (0x00010000)
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#define PRSSTAT_BREN (0x00000800)
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#define PRSSTAT_BWEN (0x00000400)
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#define PRSSTAT_SDSTB (0X00000008)
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#define PRSSTAT_DLA (0x00000004)
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#define PRSSTAT_CICHB (0x00000002)
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#define PRSSTAT_CIDHB (0x00000001)
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#define PROCTL 0x0002e028
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#define PROCTL_INIT 0x00000020
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#define PROCTL_DTW_4 0x00000002
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#define PROCTL_DTW_8 0x00000004
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#define PROCTL_D3CD 0x00000008
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#define PROCTL_DMAS_MASK 0x00000300
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#define PROCTL_DMAS_SDMA 0x00000000
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#define PROCTL_DMAS_ADMA1 0x00000100
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#define PROCTL_DMAS_ADMA2 0x00000300
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#define PROCTL_VOLT_SEL 0x00000400
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#define CMDARG 0x0002e008
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#define XFERTYP 0x0002e00c
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#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
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#define XFERTYP_CMDTYP_NORMAL 0x0
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#define XFERTYP_CMDTYP_SUSPEND 0x00400000
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#define XFERTYP_CMDTYP_RESUME 0x00800000
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#define XFERTYP_CMDTYP_ABORT 0x00c00000
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#define XFERTYP_DPSEL 0x00200000
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#define XFERTYP_CICEN 0x00100000
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#define XFERTYP_CCCEN 0x00080000
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#define XFERTYP_RSPTYP_NONE 0
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#define XFERTYP_RSPTYP_136 0x00010000
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#define XFERTYP_RSPTYP_48 0x00020000
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#define XFERTYP_RSPTYP_48_BUSY 0x00030000
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#define XFERTYP_MSBSEL 0x00000020
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#define XFERTYP_DTDSEL 0x00000010
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#define XFERTYP_DDREN 0x00000008
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#define XFERTYP_AC12EN 0x00000004
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#define XFERTYP_BCEN 0x00000002
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#define XFERTYP_DMAEN 0x00000001
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#define CINS_TIMEOUT 1000
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#define PIO_TIMEOUT 500
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#define DSADDR 0x2e004
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#define CMDRSP0 0x2e010
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#define CMDRSP1 0x2e014
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#define CMDRSP2 0x2e018
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#define CMDRSP3 0x2e01c
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#define DATPORT 0x2e020
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#define WML 0x2e044
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#define WML_WRITE 0x00010000
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#ifdef CONFIG_FSL_SDHC_V2_3
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#define WML_RD_WML_MAX 0x80
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#define WML_WR_WML_MAX 0x80
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#define WML_RD_WML_MAX_VAL 0x0
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#define WML_WR_WML_MAX_VAL 0x0
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#define WML_RD_WML_MASK 0x7f
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#define WML_WR_WML_MASK 0x7f0000
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#else
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#define WML_RD_WML_MAX 0x10
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#define WML_WR_WML_MAX 0x80
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#define WML_RD_WML_MAX_VAL 0x10
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#define WML_WR_WML_MAX_VAL 0x80
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#define WML_RD_WML_MASK 0xff
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#define WML_WR_WML_MASK 0xff0000
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#endif
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#define BLKATTR 0x2e004
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#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
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#define BLKATTR_SIZE(x) (x & 0x1fff)
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#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
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/* Auto CMD error status register / system control 2 register */
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#define EXECUTE_TUNING 0x00400000
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#define SMPCLKSEL 0x00800000
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#define UHSM_MASK 0x00070000
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#define UHSM_SDR104_HS200 0x00030000
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/* Host controller capabilities register */
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#define HOSTCAPBLT_VS18 0x04000000
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#define HOSTCAPBLT_VS30 0x02000000
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#define HOSTCAPBLT_VS33 0x01000000
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#define HOSTCAPBLT_SRS 0x00800000
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#define HOSTCAPBLT_DMAS 0x00400000
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#define HOSTCAPBLT_HSS 0x00200000
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/* Tuning block control register */
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#define TBCTL_TB_EN 0x00000004
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#define HS400_MODE 0x00000010
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#define HS400_WNDW_ADJUST 0x00000040
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/* SD clock control register */
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#define CMD_CLK_CTL 0x00008000
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/* SD timing control register */
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#define FLW_CTL_BG 0x00008000
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/* DLL config 0 register */
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#define DLL_ENABLE 0x80000000
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#define DLL_RESET 0x40000000
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#define DLL_FREQ_SEL 0x08000000
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/* DLL status 0 register */
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#define DLL_STS_SLV_LOCK 0x08000000
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#define MAX_TUNING_LOOP 40
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#define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff)
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#define VENDOR_V_10 0x00
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#define VENDOR_V_20 0x10
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#define VENDOR_V_21 0x11
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#define VENDOR_V_22 0x12
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#define VENDOR_V_23 0x13
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#define VENDOR_V_30 0x20
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#define VENDOR_V_31 0x21
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#define VENDOR_V_32 0x22
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struct fsl_esdhc_cfg {
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phys_addr_t esdhc_base;
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u32 sdhc_clk;
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u8 max_bus_width;
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int vs18_enable; /* Use 1.8V if set to 1 */
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struct mmc_config cfg;
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};
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/* Select the correct accessors depending on endianess */
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#if defined CONFIG_SYS_FSL_ESDHC_LE
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#define esdhc_read32 in_le32
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#define esdhc_write32 out_le32
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#define esdhc_clrsetbits32 clrsetbits_le32
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#define esdhc_clrbits32 clrbits_le32
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#define esdhc_setbits32 setbits_le32
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#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
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#define esdhc_read32 in_be32
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#define esdhc_write32 out_be32
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#define esdhc_clrsetbits32 clrsetbits_be32
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#define esdhc_clrbits32 clrbits_be32
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#define esdhc_setbits32 setbits_be32
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#elif __BYTE_ORDER == __LITTLE_ENDIAN
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#define esdhc_read32 in_le32
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#define esdhc_write32 out_le32
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#define esdhc_clrsetbits32 clrsetbits_le32
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#define esdhc_clrbits32 clrbits_le32
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#define esdhc_setbits32 setbits_le32
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#elif __BYTE_ORDER == __BIG_ENDIAN
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#define esdhc_read32 in_be32
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#define esdhc_write32 out_be32
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#define esdhc_clrsetbits32 clrsetbits_be32
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#define esdhc_clrbits32 clrbits_be32
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#define esdhc_setbits32 setbits_be32
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#else
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#error "Endianess is not defined: please fix to continue"
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#endif
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#ifdef CONFIG_FSL_ESDHC
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int fsl_esdhc_mmc_init(struct bd_info *bis);
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int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg);
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void fdt_fixup_esdhc(void *blob, struct bd_info *bd);
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#else
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static inline int fsl_esdhc_mmc_init(struct bd_info *bis) { return -ENOSYS; }
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static inline void fdt_fixup_esdhc(void *blob, struct bd_info *bd) {}
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#endif /* CONFIG_FSL_ESDHC */
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void __noreturn mmc_boot(void);
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void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
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#endif /* __FSL_ESDHC_H__ */
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