mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-24 20:13:39 +00:00
7d3c6c6e9f
A few minor changes:
* Get rid of leftover comments, other commits removed the defines they
referred to.
* CONFIG_SYS_NETA_INTERFACE_TYPE is not used anymore since commit
e3b9c98a23 ("net: mvneta: Convert to driver model").
* Drop CONFIG_USB_MAX_CONTROLLER_COUNT: it is per-HCI type, so XHCI and
EHCI could still both work be used.
* Unconditionally define CONFIG_EHCI_IS_TDI: it has no effect on XHCI so
that conditional doesn't make any sense.
* Define a larger PHY_ANEG_TIMEOUT: In my test bed, the NIC is directly
connected to some RTL8111 and the default 8s timeout was often too
short.
Signed-off-by: Phil Sutter <phil@nwl.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
83 lines
2 KiB
C
83 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
|
*/
|
|
|
|
#ifndef _CONFIG_SYNOLOGY_DS414_H
|
|
#define _CONFIG_SYNOLOGY_DS414_H
|
|
|
|
/*
|
|
* High Level Configuration Options (easy to change)
|
|
*/
|
|
|
|
/*
|
|
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
|
|
* for DDR ECC byte filling in the SPL before loading the main
|
|
* U-Boot into it.
|
|
*/
|
|
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
|
|
|
|
/* I2C */
|
|
#define CONFIG_SYS_I2C
|
|
#define CONFIG_SYS_I2C_MVTWSI
|
|
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
|
|
#define CONFIG_SYS_I2C_SLAVE 0x0
|
|
#define CONFIG_SYS_I2C_SPEED 100000
|
|
|
|
/* PCIe support */
|
|
#ifndef CONFIG_SPL_BUILD
|
|
#define CONFIG_PCI_SCAN_SHOW
|
|
#endif
|
|
|
|
/* USB/EHCI/XHCI configuration */
|
|
#define CONFIG_EHCI_IS_TDI
|
|
|
|
/*
|
|
* mv-common.h should be defined after CMD configs since it used them
|
|
* to enable certain macros
|
|
*/
|
|
#include "mv-common.h"
|
|
|
|
/*
|
|
* Memory layout while starting into the bin_hdr via the
|
|
* BootROM:
|
|
*
|
|
* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
|
|
* 0x4000.4030 bin_hdr start address
|
|
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
|
|
* 0x4007.fffc BootROM stack top
|
|
*
|
|
* The address space between 0x4007.fffc and 0x400f.fff is not locked in
|
|
* L2 cache thus cannot be used.
|
|
*/
|
|
|
|
/* SPL */
|
|
/* Defines for SPL */
|
|
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
|
|
|
|
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
|
|
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#define CONFIG_SYS_MALLOC_SIMPLE
|
|
#endif
|
|
|
|
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
|
|
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
|
|
|
|
#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
|
|
/* SPL related SPI defines */
|
|
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
|
|
#endif
|
|
|
|
/* DS414 bus width is 32bits */
|
|
#define CONFIG_DDR_32BIT
|
|
|
|
/* Default Environment */
|
|
#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
|
|
#define CONFIG_LOADADDR 0x80000
|
|
|
|
/* increase autoneg timeout, my NIC sucks */
|
|
#define PHY_ANEG_TIMEOUT 16000
|
|
|
|
#endif /* _CONFIG_SYNOLOGY_DS414_H */
|