mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
170 lines
3.8 KiB
C
170 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* Based on original Kirkwood support which is
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* Copyright (C) Marvell International Ltd. and its affiliates
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#define UBOOT_CNTR 0 /* counter to use for uboot timer */
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/* Timer reload and current value registers */
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struct orion5x_tmr_val {
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u32 reload; /* Timer reload reg */
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u32 val; /* Timer value reg */
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};
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/* Timer registers */
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struct orion5x_tmr_registers {
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u32 ctrl; /* Timer control reg */
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u32 pad[3];
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struct orion5x_tmr_val tmr[2];
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u32 wdt_reload;
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u32 wdt_val;
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};
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struct orion5x_tmr_registers *orion5x_tmr_regs =
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(struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
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/*
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* ARM Timers Registers Map
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*/
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#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
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#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
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#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
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/*
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* ARM Timers Control Register
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* CPU_TIMERS_CTRL_REG (CTCR)
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*/
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#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
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#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
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#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
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#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
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#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
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#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
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#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
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#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
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/*
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* ARM Timer\Watchdog Reload Register
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* CNTMR_RELOAD_REG (TRR)
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*/
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#define TRG_ARM_TIMER_REL_OFFS 0
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#define TRG_ARM_TIMER_REL_MASK 0xffffffff
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/*
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* ARM Timer\Watchdog Register
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* CNTMR_VAL_REG (TVRG)
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*/
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#define TVR_ARM_TIMER_OFFS 0
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#define TVR_ARM_TIMER_MASK 0xffffffff
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#define TVR_ARM_TIMER_MAX 0xffffffff
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#define TIMER_LOAD_VAL 0xffffffff
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static inline ulong read_timer(void)
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{
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return readl(CNTMR_VAL_REG(UBOOT_CNTR))
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/ (CONFIG_SYS_TCLK / 1000);
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}
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DECLARE_GLOBAL_DATA_PTR;
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#define timestamp gd->arch.tbl
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#define lastdec gd->arch.lastinc
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ulong get_timer_masked(void)
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{
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ulong now = read_timer();
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if (lastdec >= now) {
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/* normal mode */
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timestamp += lastdec - now;
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} else {
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/* we have an overflow ... */
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timestamp += lastdec +
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(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
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}
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lastdec = now;
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return timestamp;
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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static inline ulong uboot_cntr_val(void)
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{
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return readl(CNTMR_VAL_REG(UBOOT_CNTR));
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}
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void __udelay(unsigned long usec)
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{
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uint current;
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ulong delayticks;
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current = uboot_cntr_val();
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delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
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if (current < delayticks) {
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delayticks -= current;
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while (uboot_cntr_val() < current)
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;
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while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
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;
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} else {
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while (uboot_cntr_val() > (current - delayticks))
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;
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}
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}
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/*
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* init the counter
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*/
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int timer_init(void)
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{
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unsigned int cntmrctrl;
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/* load value into timer */
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writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
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writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
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/* enable timer in auto reload mode */
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cntmrctrl = readl(CNTMR_CTRL_REG);
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cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
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cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
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writel(cntmrctrl, CNTMR_CTRL_REG);
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return 0;
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}
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void timer_init_r(void)
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{
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/* init the timestamp and lastdec value */
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lastdec = read_timer();
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timestamp = 0;
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk (void)
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{
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return (ulong)CONFIG_SYS_HZ;
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}
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