mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
69492fb4c5
Move the sg_set_pinsel macro to arch/arm/mach-uniphier/arm32/debug_ll.S
since it is not used anywhere else.
Move the C functions sg_set_{pinsel,iectrl} to debug-uart.c since they
are not used anywhere else.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
90 lines
3.3 KiB
C
90 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* UniPhier SG (SoC Glue) block registers
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*
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* Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
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* Copyright (C) 2016-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#ifndef UNIPHIER_SG_REGS_H
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#define UNIPHIER_SG_REGS_H
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/* Base Address */
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#define SG_CTRL_BASE 0x5f800000
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#define SG_DBG_BASE 0x5f900000
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/* Revision */
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#define SG_REVISION (SG_CTRL_BASE | 0x0000)
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/* Memory Configuration */
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#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
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#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
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#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
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#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
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#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
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#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
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#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
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#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
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#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
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#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
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#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
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#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
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#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
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#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
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#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
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#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
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#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
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#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
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#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
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#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
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#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
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#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
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#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
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#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
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#define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16))
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#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
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#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
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#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
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/* PH1-LD6b, ProXstream2, PH1-LD20 only */
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#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
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#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
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#define SG_USBPHYCTRL (SG_CTRL_BASE | 0x500)
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#define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554)
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#define SG_ETPHYCNT (SG_CTRL_BASE | 0x550)
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/* Pin Control */
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#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
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/* PH1-Pro4, PH1-Pro5 */
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#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
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/* Input Enable */
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#define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
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/* Pin Monitor */
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#define SG_PINMON0 (SG_DBG_BASE | 0x0100)
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#define SG_PINMON2 (SG_DBG_BASE | 0x0108)
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#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
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#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
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#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
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#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
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#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
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#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
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#endif /* UNIPHIER_SG_REGS_H */
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