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https://github.com/AsahiLinux/u-boot
synced 2024-12-14 15:23:07 +00:00
7a49d61742
This patch adds support for MTK SPI NOR controller, which you can see on mt7622 & mt7629. 1. This controller is designed only for SPI NOR. We can't adjust its bus clock dynamically. Set clock in dts instead. 2. This controller only supports 1-1-1 write mode. 3. Remove mtk_snor_match_read() since upper SPI-MEM layer already handles command. 4. sf read/write/update commands are tested with this driver. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
563 lines
14 KiB
C
563 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Mediatek SPI-NOR controller driver
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//
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// Copyright (C) 2020 SkyLake Huang <SkyLake.Huang@mediatek.com>
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//
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// Some parts are based on drivers/spi/spi-mtk-nor.c of linux version
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#include <clk.h>
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <dm/device.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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#include <linux/completion.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <stdbool.h>
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#include <watchdog.h>
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#include <linux/dma-mapping.h>
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#define DRIVER_NAME "mtk-spi-nor"
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#define MTK_NOR_REG_CMD 0x00
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#define MTK_NOR_CMD_WRSR BIT(5)
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#define MTK_NOR_CMD_WRITE BIT(4)
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#define MTK_NOR_CMD_PROGRAM BIT(2)
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#define MTK_NOR_CMD_RDSR BIT(1)
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#define MTK_NOR_CMD_READ BIT(0)
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#define MTK_NOR_CMD_MASK GENMASK(5, 0)
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#define MTK_NOR_REG_PRG_CNT 0x04
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#define MTK_NOR_REG_RDSR 0x08
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#define MTK_NOR_REG_RDATA 0x0c
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#define MTK_NOR_REG_RADR0 0x10
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#define MTK_NOR_REG_RADR(n) (MTK_NOR_REG_RADR0 + 4 * (n))
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#define MTK_NOR_REG_RADR3 0xc8
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#define MTK_NOR_REG_WDATA 0x1c
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#define MTK_NOR_REG_PRGDATA0 0x20
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#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n))
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#define MTK_NOR_REG_PRGDATA_MAX 5
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#define MTK_NOR_REG_SHIFT0 0x38
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#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n))
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#define MTK_NOR_REG_SHIFT_MAX 9
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#define MTK_NOR_REG_CFG1 0x60
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#define MTK_NOR_FAST_READ BIT(0)
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#define MTK_NOR_REG_CFG2 0x64
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#define MTK_NOR_WR_CUSTOM_OP_EN BIT(4)
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#define MTK_NOR_WR_BUF_EN BIT(0)
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#define MTK_NOR_REG_PP_DATA 0x98
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#define MTK_NOR_REG_IRQ_STAT 0xa8
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#define MTK_NOR_REG_IRQ_EN 0xac
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#define MTK_NOR_IRQ_DMA BIT(7)
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#define MTK_NOR_IRQ_WRSR BIT(5)
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#define MTK_NOR_IRQ_MASK GENMASK(7, 0)
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#define MTK_NOR_REG_CFG3 0xb4
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#define MTK_NOR_DISABLE_WREN BIT(7)
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#define MTK_NOR_DISABLE_SR_POLL BIT(5)
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#define MTK_NOR_REG_WP 0xc4
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#define MTK_NOR_ENABLE_SF_CMD 0x30
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#define MTK_NOR_REG_BUSCFG 0xcc
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#define MTK_NOR_4B_ADDR BIT(4)
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#define MTK_NOR_QUAD_ADDR BIT(3)
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#define MTK_NOR_QUAD_READ BIT(2)
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#define MTK_NOR_DUAL_ADDR BIT(1)
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#define MTK_NOR_DUAL_READ BIT(0)
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#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0)
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#define MTK_NOR_REG_DMA_CTL 0x718
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#define MTK_NOR_DMA_START BIT(0)
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#define MTK_NOR_REG_DMA_FADR 0x71c
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#define MTK_NOR_REG_DMA_DADR 0x720
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#define MTK_NOR_REG_DMA_END_DADR 0x724
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#define MTK_NOR_PRG_MAX_SIZE 6
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// Reading DMA src/dst addresses have to be 16-byte aligned
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#define MTK_NOR_DMA_ALIGN 16
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#define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
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// and we allocate a bounce buffer if destination address isn't aligned.
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#define MTK_NOR_BOUNCE_BUF_SIZE PAGE_SIZE
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// Buffered page program can do one 128-byte transfer
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#define MTK_NOR_PP_SIZE 128
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#define CLK_TO_US(priv, clkcnt) DIV_ROUND_UP(clkcnt, (priv)->spi_freq / 1000000)
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#define MTK_NOR_UNLOCK_ALL 0x0
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struct mtk_snor_priv {
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struct device *dev;
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void __iomem *base;
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u8 *buffer;
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struct clk spi_clk;
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struct clk ctlr_clk;
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unsigned int spi_freq;
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bool wbuf_en;
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};
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static inline void mtk_snor_rmw(struct mtk_snor_priv *priv, u32 reg, u32 set,
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u32 clr)
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{
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u32 val = readl(priv->base + reg);
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val &= ~clr;
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val |= set;
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writel(val, priv->base + reg);
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}
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static inline int mtk_snor_cmd_exec(struct mtk_snor_priv *priv, u32 cmd,
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ulong clk)
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{
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unsigned long long delay = CLK_TO_US(priv, clk);
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u32 reg;
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int ret;
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writel(cmd, priv->base + MTK_NOR_REG_CMD);
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delay = (delay + 1) * 200;
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ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CMD, reg,
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!(reg & cmd), delay);
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if (ret < 0)
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dev_err(priv->dev, "command %u timeout.\n", cmd);
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return ret;
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}
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static void mtk_snor_set_addr(struct mtk_snor_priv *priv,
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const struct spi_mem_op *op)
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{
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u32 addr = op->addr.val;
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int i;
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for (i = 0; i < 3; i++) {
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writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR(i));
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addr >>= 8;
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}
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if (op->addr.nbytes == 4) {
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writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR3);
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mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0);
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} else {
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mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR);
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}
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}
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static bool need_bounce(const struct spi_mem_op *op)
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{
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return ((uintptr_t)op->data.buf.in & MTK_NOR_DMA_ALIGN_MASK);
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}
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static int mtk_snor_adjust_op_size(struct spi_slave *slave,
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struct spi_mem_op *op)
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{
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if (!op->data.nbytes)
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return 0;
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if (op->addr.nbytes == 3 || op->addr.nbytes == 4) {
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if (op->data.dir == SPI_MEM_DATA_IN) { //&&
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// limit size to prevent timeout calculation overflow
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if (op->data.nbytes > 0x400000)
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op->data.nbytes = 0x400000;
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if (op->addr.val & MTK_NOR_DMA_ALIGN_MASK ||
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op->data.nbytes < MTK_NOR_DMA_ALIGN)
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op->data.nbytes = 1;
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else if (!need_bounce(op))
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op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK;
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else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE)
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op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE;
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return 0;
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} else if (op->data.dir == SPI_MEM_DATA_OUT) {
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if (op->data.nbytes >= MTK_NOR_PP_SIZE)
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op->data.nbytes = MTK_NOR_PP_SIZE;
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else
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op->data.nbytes = 1;
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return 0;
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}
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}
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return 0;
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}
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static bool mtk_snor_supports_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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/* This controller only supports 1-1-1 write mode */
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if (op->data.dir == SPI_MEM_DATA_OUT &&
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(op->cmd.buswidth != 1 || op->data.buswidth != 1))
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return false;
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return true;
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}
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static void mtk_snor_setup_bus(struct mtk_snor_priv *priv,
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const struct spi_mem_op *op)
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{
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u32 reg = 0;
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if (op->addr.nbytes == 4)
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reg |= MTK_NOR_4B_ADDR;
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if (op->data.buswidth == 4) {
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reg |= MTK_NOR_QUAD_READ;
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writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(4));
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if (op->addr.buswidth == 4)
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reg |= MTK_NOR_QUAD_ADDR;
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} else if (op->data.buswidth == 2) {
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reg |= MTK_NOR_DUAL_READ;
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writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(3));
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if (op->addr.buswidth == 2)
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reg |= MTK_NOR_DUAL_ADDR;
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} else {
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if (op->cmd.opcode == 0x0b)
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mtk_snor_rmw(priv, MTK_NOR_REG_CFG1, MTK_NOR_FAST_READ,
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0);
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else
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mtk_snor_rmw(priv, MTK_NOR_REG_CFG1, 0,
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MTK_NOR_FAST_READ);
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}
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mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, reg, MTK_NOR_BUS_MODE_MASK);
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}
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static int mtk_snor_dma_exec(struct mtk_snor_priv *priv, u32 from,
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unsigned int length, dma_addr_t dma_addr)
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{
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int ret = 0;
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ulong delay;
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u32 reg;
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writel(from, priv->base + MTK_NOR_REG_DMA_FADR);
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writel(dma_addr, priv->base + MTK_NOR_REG_DMA_DADR);
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writel(dma_addr + length, priv->base + MTK_NOR_REG_DMA_END_DADR);
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mtk_snor_rmw(priv, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
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delay = CLK_TO_US(priv, (length + 5) * BITS_PER_BYTE);
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delay = (delay + 1) * 100;
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ret = readl_poll_timeout(priv->base + MTK_NOR_REG_DMA_CTL, reg,
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!(reg & MTK_NOR_DMA_START), delay);
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if (ret < 0)
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dev_err(priv->dev, "dma read timeout.\n");
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return ret;
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}
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static int mtk_snor_read_bounce(struct mtk_snor_priv *priv,
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const struct spi_mem_op *op)
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{
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unsigned int rdlen;
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int ret;
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if (op->data.nbytes & MTK_NOR_DMA_ALIGN_MASK)
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rdlen = (op->data.nbytes + MTK_NOR_DMA_ALIGN) &
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~MTK_NOR_DMA_ALIGN_MASK;
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else
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rdlen = op->data.nbytes;
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ret = mtk_snor_dma_exec(priv, op->addr.val, rdlen,
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(dma_addr_t)priv->buffer);
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if (!ret)
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memcpy(op->data.buf.in, priv->buffer, op->data.nbytes);
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return ret;
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}
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static int mtk_snor_read_dma(struct mtk_snor_priv *priv,
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const struct spi_mem_op *op)
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{
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int ret;
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dma_addr_t dma_addr;
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if (need_bounce(op))
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return mtk_snor_read_bounce(priv, op);
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dma_addr = dma_map_single(op->data.buf.in, op->data.nbytes,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(priv->dev, dma_addr))
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return -EINVAL;
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ret = mtk_snor_dma_exec(priv, op->addr.val, op->data.nbytes, dma_addr);
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dma_unmap_single(dma_addr, op->data.nbytes, DMA_FROM_DEVICE);
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return ret;
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}
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static int mtk_snor_read_pio(struct mtk_snor_priv *priv,
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const struct spi_mem_op *op)
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{
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u8 *buf = op->data.buf.in;
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int ret;
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ret = mtk_snor_cmd_exec(priv, MTK_NOR_CMD_READ, 6 * BITS_PER_BYTE);
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if (!ret)
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buf[0] = readb(priv->base + MTK_NOR_REG_RDATA);
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return ret;
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}
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static int mtk_snor_write_buffer_enable(struct mtk_snor_priv *priv)
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{
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int ret;
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u32 val;
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if (priv->wbuf_en)
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return 0;
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val = readl(priv->base + MTK_NOR_REG_CFG2);
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writel(val | MTK_NOR_WR_BUF_EN, priv->base + MTK_NOR_REG_CFG2);
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ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CFG2, val,
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val & MTK_NOR_WR_BUF_EN, 10000);
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if (!ret)
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priv->wbuf_en = true;
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return ret;
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}
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static int mtk_snor_write_buffer_disable(struct mtk_snor_priv *priv)
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{
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int ret;
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u32 val;
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if (!priv->wbuf_en)
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return 0;
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val = readl(priv->base + MTK_NOR_REG_CFG2);
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writel(val & ~MTK_NOR_WR_BUF_EN, priv->base + MTK_NOR_REG_CFG2);
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ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CFG2, val,
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!(val & MTK_NOR_WR_BUF_EN), 10000);
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if (!ret)
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priv->wbuf_en = false;
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return ret;
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}
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static int mtk_snor_pp_buffered(struct mtk_snor_priv *priv,
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const struct spi_mem_op *op)
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{
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const u8 *buf = op->data.buf.out;
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u32 val;
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int ret, i;
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ret = mtk_snor_write_buffer_enable(priv);
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if (ret < 0)
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return ret;
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for (i = 0; i < op->data.nbytes; i += 4) {
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val = buf[i + 3] << 24 | buf[i + 2] << 16 | buf[i + 1] << 8 |
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buf[i];
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writel(val, priv->base + MTK_NOR_REG_PP_DATA);
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}
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mtk_snor_cmd_exec(priv, MTK_NOR_CMD_WRITE,
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(op->data.nbytes + 5) * BITS_PER_BYTE);
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return mtk_snor_write_buffer_disable(priv);
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}
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static int mtk_snor_pp_unbuffered(struct mtk_snor_priv *priv,
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const struct spi_mem_op *op)
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{
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const u8 *buf = op->data.buf.out;
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int ret;
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ret = mtk_snor_write_buffer_disable(priv);
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if (ret < 0)
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return ret;
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writeb(buf[0], priv->base + MTK_NOR_REG_WDATA);
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return mtk_snor_cmd_exec(priv, MTK_NOR_CMD_WRITE, 6 * BITS_PER_BYTE);
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}
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static int mtk_snor_cmd_program(struct mtk_snor_priv *priv,
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const struct spi_mem_op *op)
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{
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u32 tx_len = 0;
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u32 trx_len = 0;
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int reg_offset = MTK_NOR_REG_PRGDATA_MAX;
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void __iomem *reg;
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u8 *txbuf;
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int tx_cnt = 0;
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u8 *rxbuf = op->data.buf.in;
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int i = 0;
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tx_len = 1 + op->addr.nbytes + op->dummy.nbytes;
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trx_len = tx_len + op->data.nbytes;
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if (op->data.dir == SPI_MEM_DATA_OUT)
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tx_len += op->data.nbytes;
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txbuf = kmalloc_array(tx_len, sizeof(u8), GFP_KERNEL);
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memset(txbuf, 0x0, tx_len * sizeof(u8));
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/* Join all bytes to be transferred */
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txbuf[tx_cnt] = op->cmd.opcode;
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tx_cnt++;
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for (i = op->addr.nbytes; i > 0; i--, tx_cnt++)
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txbuf[tx_cnt] = ((u8 *)&op->addr.val)[i - 1];
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for (i = op->dummy.nbytes; i > 0; i--, tx_cnt++)
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txbuf[tx_cnt] = 0x0;
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if (op->data.dir == SPI_MEM_DATA_OUT)
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for (i = op->data.nbytes; i > 0; i--, tx_cnt++)
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txbuf[tx_cnt] = ((u8 *)op->data.buf.out)[i - 1];
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for (i = MTK_NOR_REG_PRGDATA_MAX; i >= 0; i--)
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writeb(0, priv->base + MTK_NOR_REG_PRGDATA(i));
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for (i = 0; i < tx_len; i++, reg_offset--)
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writeb(txbuf[i], priv->base + MTK_NOR_REG_PRGDATA(reg_offset));
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kfree(txbuf);
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writel(trx_len * BITS_PER_BYTE, priv->base + MTK_NOR_REG_PRG_CNT);
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mtk_snor_cmd_exec(priv, MTK_NOR_CMD_PROGRAM, trx_len * BITS_PER_BYTE);
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reg_offset = op->data.nbytes - 1;
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for (i = 0; i < op->data.nbytes; i++, reg_offset--) {
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reg = priv->base + MTK_NOR_REG_SHIFT(reg_offset);
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rxbuf[i] = readb(reg);
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}
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return 0;
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}
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static int mtk_snor_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct udevice *bus = dev_get_parent(slave->dev);
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struct mtk_snor_priv *priv = dev_get_priv(bus);
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int ret;
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if (op->data.dir == SPI_MEM_NO_DATA || op->addr.nbytes == 0) {
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return mtk_snor_cmd_program(priv, op);
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} else if (op->data.dir == SPI_MEM_DATA_OUT) {
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mtk_snor_set_addr(priv, op);
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writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA0);
|
|
if (op->data.nbytes == MTK_NOR_PP_SIZE)
|
|
return mtk_snor_pp_buffered(priv, op);
|
|
return mtk_snor_pp_unbuffered(priv, op);
|
|
} else if (op->data.dir == SPI_MEM_DATA_IN) {
|
|
ret = mtk_snor_write_buffer_disable(priv);
|
|
if (ret < 0)
|
|
return ret;
|
|
mtk_snor_setup_bus(priv, op);
|
|
if (op->data.nbytes == 1) {
|
|
mtk_snor_set_addr(priv, op);
|
|
return mtk_snor_read_pio(priv, op);
|
|
} else {
|
|
return mtk_snor_read_dma(priv, op);
|
|
}
|
|
}
|
|
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
static int mtk_snor_probe(struct udevice *bus)
|
|
{
|
|
struct mtk_snor_priv *priv = dev_get_priv(bus);
|
|
u8 *buffer;
|
|
int ret;
|
|
u32 reg;
|
|
|
|
priv->base = (void __iomem *)devfdt_get_addr(bus);
|
|
if (!priv->base)
|
|
return -EINVAL;
|
|
|
|
ret = clk_get_by_name(bus, "spi", &priv->spi_clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = clk_get_by_name(bus, "sf", &priv->ctlr_clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
buffer = devm_kmalloc(bus, MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
|
|
GFP_KERNEL);
|
|
if (!buffer)
|
|
return -ENOMEM;
|
|
if ((ulong)buffer & MTK_NOR_DMA_ALIGN_MASK)
|
|
buffer = (u8 *)(((ulong)buffer + MTK_NOR_DMA_ALIGN) &
|
|
~MTK_NOR_DMA_ALIGN_MASK);
|
|
priv->buffer = buffer;
|
|
|
|
clk_enable(&priv->spi_clk);
|
|
clk_enable(&priv->ctlr_clk);
|
|
|
|
priv->spi_freq = clk_get_rate(&priv->spi_clk);
|
|
printf("spi frequency: %d Hz\n", priv->spi_freq);
|
|
|
|
/* With this setting, we issue one command at a time to
|
|
* accommodate to SPI-mem framework.
|
|
*/
|
|
writel(MTK_NOR_ENABLE_SF_CMD, priv->base + MTK_NOR_REG_WP);
|
|
mtk_snor_rmw(priv, MTK_NOR_REG_CFG2, MTK_NOR_WR_CUSTOM_OP_EN, 0);
|
|
mtk_snor_rmw(priv, MTK_NOR_REG_CFG3,
|
|
MTK_NOR_DISABLE_WREN | MTK_NOR_DISABLE_SR_POLL, 0);
|
|
|
|
/* Unlock all blocks using write status command.
|
|
* SPI-MEM hasn't implemented unlock procedure on MXIC devices.
|
|
* We may remove this later.
|
|
*/
|
|
writel(2 * BITS_PER_BYTE, priv->base + MTK_NOR_REG_PRG_CNT);
|
|
writel(MTK_NOR_UNLOCK_ALL, priv->base + MTK_NOR_REG_PRGDATA(5));
|
|
writel(MTK_NOR_IRQ_WRSR, priv->base + MTK_NOR_REG_IRQ_EN);
|
|
writel(MTK_NOR_CMD_WRSR, priv->base + MTK_NOR_REG_CMD);
|
|
ret = readl_poll_timeout(priv->base + MTK_NOR_REG_IRQ_STAT, reg,
|
|
!(reg & MTK_NOR_IRQ_WRSR),
|
|
((3 * BITS_PER_BYTE) + 1) * 200);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_snor_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
/* MTK's SNOR controller does not have a bus clock divider.
|
|
* We setup maximum bus clock in dts.
|
|
*/
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_snor_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
/* We set up mode later for each transmission.
|
|
*/
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops mtk_snor_mem_ops = {
|
|
.adjust_op_size = mtk_snor_adjust_op_size,
|
|
.supports_op = mtk_snor_supports_op,
|
|
.exec_op = mtk_snor_exec_op
|
|
};
|
|
|
|
static const struct dm_spi_ops mtk_snor_ops = {
|
|
.mem_ops = &mtk_snor_mem_ops,
|
|
.set_speed = mtk_snor_set_speed,
|
|
.set_mode = mtk_snor_set_mode,
|
|
};
|
|
|
|
static const struct udevice_id mtk_snor_ids[] = {
|
|
{ .compatible = "mediatek,mtk-snor" },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(mtk_snor) = {
|
|
.name = "mtk_snor",
|
|
.id = UCLASS_SPI,
|
|
.of_match = mtk_snor_ids,
|
|
.ops = &mtk_snor_ops,
|
|
.priv_auto = sizeof(struct mtk_snor_priv),
|
|
.probe = mtk_snor_probe,
|
|
};
|