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72a087e047
Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
204 lines
5.2 KiB
C
204 lines
5.2 KiB
C
/*
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* Register definitions for System Manager
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*/
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#ifndef __CPU_AT32AP_SM_H__
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#define __CPU_AT32AP_SM_H__
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/* SM register offsets */
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#define SM_PM_MCCTRL 0x0000
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#define SM_PM_CKSEL 0x0004
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#define SM_PM_CPU_MASK 0x0008
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#define SM_PM_HSB_MASK 0x000c
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#define SM_PM_PBA_MASK 0x0010
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#define SM_PM_PBB_MASK 0x0014
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#define SM_PM_PLL0 0x0020
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#define SM_PM_PLL1 0x0024
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#define SM_PM_VCTRL 0x0030
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#define SM_PM_VMREF 0x0034
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#define SM_PM_VMV 0x0038
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#define SM_PM_IER 0x0040
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#define SM_PM_IDR 0x0044
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#define SM_PM_IMR 0x0048
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#define SM_PM_ISR 0x004c
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#define SM_PM_ICR 0x0050
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#define SM_PM_GCCTRL 0x0060
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#define SM_RTC_CTRL 0x0080
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#define SM_RTC_VAL 0x0084
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#define SM_RTC_TOP 0x0088
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#define SM_RTC_IER 0x0090
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#define SM_RTC_IDR 0x0094
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#define SM_RTC_IMR 0x0098
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#define SM_RTC_ISR 0x009c
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#define SM_RTC_ICR 0x00a0
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#define SM_WDT_CTRL 0x00b0
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#define SM_WDT_CLR 0x00b4
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#define SM_WDT_EXT 0x00b8
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#define SM_RC_RCAUSE 0x00c0
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#define SM_EIM_IER 0x0100
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#define SM_EIM_IDR 0x0104
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#define SM_EIM_IMR 0x0108
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#define SM_EIM_ISR 0x010c
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#define SM_EIM_ICR 0x0110
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#define SM_EIM_MODE 0x0114
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#define SM_EIM_EDGE 0x0118
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#define SM_EIM_LEVEL 0x011c
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#define SM_EIM_TEST 0x0120
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#define SM_EIM_NMIC 0x0124
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/* Bitfields in PM_CKSEL */
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#define SM_CPUSEL_OFFSET 0
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#define SM_CPUSEL_SIZE 3
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#define SM_CPUDIV_OFFSET 7
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#define SM_CPUDIV_SIZE 1
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#define SM_HSBSEL_OFFSET 8
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#define SM_HSBSEL_SIZE 3
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#define SM_HSBDIV_OFFSET 15
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#define SM_HSBDIV_SIZE 1
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#define SM_PBASEL_OFFSET 16
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#define SM_PBASEL_SIZE 3
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#define SM_PBADIV_OFFSET 23
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#define SM_PBADIV_SIZE 1
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#define SM_PBBSEL_OFFSET 24
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#define SM_PBBSEL_SIZE 3
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#define SM_PBBDIV_OFFSET 31
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#define SM_PBBDIV_SIZE 1
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/* Bitfields in PM_PLL0 */
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#define SM_PLLEN_OFFSET 0
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#define SM_PLLEN_SIZE 1
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#define SM_PLLOSC_OFFSET 1
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#define SM_PLLOSC_SIZE 1
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#define SM_PLLOPT_OFFSET 2
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#define SM_PLLOPT_SIZE 3
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#define SM_PLLDIV_OFFSET 8
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#define SM_PLLDIV_SIZE 8
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#define SM_PLLMUL_OFFSET 16
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#define SM_PLLMUL_SIZE 8
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#define SM_PLLCOUNT_OFFSET 24
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#define SM_PLLCOUNT_SIZE 6
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#define SM_PLLTEST_OFFSET 31
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#define SM_PLLTEST_SIZE 1
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/* Bitfields in PM_VCTRL */
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#define SM_VAUTO_OFFSET 0
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#define SM_VAUTO_SIZE 1
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#define SM_PM_VCTRL_VAL_OFFSET 8
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#define SM_PM_VCTRL_VAL_SIZE 7
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/* Bitfields in PM_VMREF */
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#define SM_REFSEL_OFFSET 0
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#define SM_REFSEL_SIZE 4
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/* Bitfields in PM_VMV */
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#define SM_PM_VMV_VAL_OFFSET 0
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#define SM_PM_VMV_VAL_SIZE 8
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/* Bitfields in PM_ICR */
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#define SM_LOCK0_OFFSET 0
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#define SM_LOCK0_SIZE 1
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#define SM_LOCK1_OFFSET 1
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#define SM_LOCK1_SIZE 1
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#define SM_WAKE_OFFSET 2
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#define SM_WAKE_SIZE 1
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#define SM_VOK_OFFSET 3
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#define SM_VOK_SIZE 1
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#define SM_VMRDY_OFFSET 4
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#define SM_VMRDY_SIZE 1
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#define SM_CKRDY_OFFSET 5
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#define SM_CKRDY_SIZE 1
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/* Bitfields in PM_GCCTRL */
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#define SM_OSCSEL_OFFSET 0
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#define SM_OSCSEL_SIZE 1
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#define SM_PLLSEL_OFFSET 1
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#define SM_PLLSEL_SIZE 1
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#define SM_CEN_OFFSET 2
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#define SM_CEN_SIZE 1
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#define SM_CPC_OFFSET 3
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#define SM_CPC_SIZE 1
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#define SM_DIVEN_OFFSET 4
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#define SM_DIVEN_SIZE 1
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#define SM_DIV_OFFSET 8
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#define SM_DIV_SIZE 8
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/* Bitfields in RTC_CTRL */
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#define SM_PCLR_OFFSET 1
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#define SM_PCLR_SIZE 1
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#define SM_TOPEN_OFFSET 2
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#define SM_TOPEN_SIZE 1
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#define SM_CLKEN_OFFSET 3
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#define SM_CLKEN_SIZE 1
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#define SM_PSEL_OFFSET 8
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#define SM_PSEL_SIZE 16
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/* Bitfields in RTC_VAL */
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#define SM_RTC_VAL_VAL_OFFSET 0
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#define SM_RTC_VAL_VAL_SIZE 31
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/* Bitfields in RTC_TOP */
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#define SM_RTC_TOP_VAL_OFFSET 0
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#define SM_RTC_TOP_VAL_SIZE 32
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/* Bitfields in RTC_ICR */
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#define SM_TOPI_OFFSET 0
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#define SM_TOPI_SIZE 1
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/* Bitfields in WDT_CTRL */
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#define SM_KEY_OFFSET 24
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#define SM_KEY_SIZE 8
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/* Bitfields in RC_RCAUSE */
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#define SM_POR_OFFSET 0
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#define SM_POR_SIZE 1
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#define SM_BOD_OFFSET 1
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#define SM_BOD_SIZE 1
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#define SM_EXT_OFFSET 2
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#define SM_EXT_SIZE 1
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#define SM_WDT_OFFSET 3
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#define SM_WDT_SIZE 1
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#define SM_NTAE_OFFSET 4
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#define SM_NTAE_SIZE 1
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#define SM_SERP_OFFSET 5
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#define SM_SERP_SIZE 1
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/* Bitfields in EIM_EDGE */
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#define SM_INT0_OFFSET 0
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#define SM_INT0_SIZE 1
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#define SM_INT1_OFFSET 1
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#define SM_INT1_SIZE 1
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#define SM_INT2_OFFSET 2
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#define SM_INT2_SIZE 1
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#define SM_INT3_OFFSET 3
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#define SM_INT3_SIZE 1
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/* Bitfields in EIM_LEVEL */
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/* Bitfields in EIM_TEST */
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#define SM_TESTEN_OFFSET 31
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#define SM_TESTEN_SIZE 1
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/* Bitfields in EIM_NMIC */
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#define SM_EN_OFFSET 0
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#define SM_EN_SIZE 1
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/* Bit manipulation macros */
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#define SM_BIT(name) \
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(1 << SM_##name##_OFFSET)
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#define SM_BF(name,value) \
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(((value) & ((1 << SM_##name##_SIZE) - 1)) \
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<< SM_##name##_OFFSET)
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#define SM_BFEXT(name,value) \
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(((value) >> SM_##name##_OFFSET) \
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& ((1 << SM_##name##_SIZE) - 1))
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#define SM_BFINS(name,value,old) \
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(((old) & ~(((1 << SM_##name##_SIZE) - 1) \
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<< SM_##name##_OFFSET)) \
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| SM_BF(name,value))
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/* Register access macros */
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#define sm_readl(port,reg) \
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readl((port)->regs + SM_##reg)
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#define sm_writel(port,reg,value) \
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writel((value), (port)->regs + SM_##reg)
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#endif /* __CPU_AT32AP_SM_H__ */
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