mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
7b9e980e87
Use spl alternate boot device feature to define fallback to the main boot device as it is defined by hardware. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
367 lines
8.5 KiB
C
367 lines
8.5 KiB
C
/*
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* SPL specific code for Compulab CM-FX6 board
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*
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* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
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*
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* Author: Nikita Kiryanov <nikita@compulab.co.il>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <fsl_esdhc.h>
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#include "common.h"
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DECLARE_GLOBAL_DATA_PTR;
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enum ddr_config {
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DDR_16BIT_256MB,
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DDR_32BIT_512MB,
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DDR_32BIT_1GB,
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DDR_64BIT_1GB,
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DDR_64BIT_2GB,
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DDR_64BIT_4GB,
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DDR_UNKNOWN,
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};
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/*
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* Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
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* Freescale QRM, but this is exactly the value used by the automatic
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* calibration script and it works also in all our tests, so we leave
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* it as is at this point.
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*/
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#define CM_FX6_DDR_IOMUX_CFG \
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.dram_sdqs0 = 0x00000038, \
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.dram_sdqs1 = 0x00000038, \
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.dram_sdqs2 = 0x00000038, \
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.dram_sdqs3 = 0x00000038, \
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.dram_sdqs4 = 0x00000038, \
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.dram_sdqs5 = 0x00000038, \
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.dram_sdqs6 = 0x00000038, \
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.dram_sdqs7 = 0x00000038, \
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.dram_dqm0 = 0x00000038, \
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.dram_dqm1 = 0x00000038, \
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.dram_dqm2 = 0x00000038, \
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.dram_dqm3 = 0x00000038, \
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.dram_dqm4 = 0x00000038, \
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.dram_dqm5 = 0x00000038, \
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.dram_dqm6 = 0x00000038, \
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.dram_dqm7 = 0x00000038, \
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.dram_cas = 0x00000038, \
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.dram_ras = 0x00000038, \
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.dram_sdclk_0 = 0x00000038, \
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.dram_sdclk_1 = 0x00000038, \
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.dram_sdcke0 = 0x00003000, \
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.dram_sdcke1 = 0x00003000, \
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.dram_reset = 0x00000038, \
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.dram_sdba2 = 0x00000000, \
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.dram_sdodt0 = 0x00000038, \
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.dram_sdodt1 = 0x00000038,
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#define CM_FX6_GPR_IOMUX_CFG \
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.grp_b0ds = 0x00000038, \
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.grp_b1ds = 0x00000038, \
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.grp_b2ds = 0x00000038, \
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.grp_b3ds = 0x00000038, \
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.grp_b4ds = 0x00000038, \
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.grp_b5ds = 0x00000038, \
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.grp_b6ds = 0x00000038, \
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.grp_b7ds = 0x00000038, \
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.grp_addds = 0x00000038, \
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.grp_ddrmode_ctl = 0x00020000, \
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.grp_ddrpke = 0x00000000, \
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.grp_ddrmode = 0x00020000, \
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.grp_ctlds = 0x00000038, \
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.grp_ddr_type = 0x000C0000,
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static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
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static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
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static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
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static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
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static struct mx6_mmdc_calibration cm_fx6_calib_s = {
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.p0_mpwldectrl0 = 0x005B0061,
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.p0_mpwldectrl1 = 0x004F0055,
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.p0_mpdgctrl0 = 0x0314030C,
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.p0_mpdgctrl1 = 0x025C0268,
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.p0_mprddlctl = 0x42464646,
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.p0_mpwrdlctl = 0x36322C34,
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};
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static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
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.cs1_mirror = 1,
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.cs_density = 16,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 1,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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};
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static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
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.mem_speed = 800,
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.density = 4,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1800,
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.trcmin = 5200,
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.trasmin = 3600,
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.SRT = 0,
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};
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static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
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{
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if (reset)
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((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
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switch (dram_config) {
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case DDR_16BIT_256MB:
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cm_fx6_sysinfo_s.dsize = 0;
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cm_fx6_sysinfo_s.ncs = 1;
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break;
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case DDR_32BIT_512MB:
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cm_fx6_sysinfo_s.dsize = 1;
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cm_fx6_sysinfo_s.ncs = 1;
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break;
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case DDR_32BIT_1GB:
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cm_fx6_sysinfo_s.dsize = 1;
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cm_fx6_sysinfo_s.ncs = 2;
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break;
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default:
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puts("Tried to setup invalid DDR configuration\n");
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hang();
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}
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mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
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udelay(100);
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}
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static struct mx6_mmdc_calibration cm_fx6_calib_q = {
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.p0_mpwldectrl0 = 0x00630068,
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.p0_mpwldectrl1 = 0x0068005D,
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.p0_mpdgctrl0 = 0x04140428,
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.p0_mpdgctrl1 = 0x037C037C,
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.p0_mprddlctl = 0x3C30303A,
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.p0_mpwrdlctl = 0x3A344038,
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.p1_mpwldectrl0 = 0x0035004C,
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.p1_mpwldectrl1 = 0x00170026,
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.p1_mpdgctrl0 = 0x0374037C,
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.p1_mpdgctrl1 = 0x0350032C,
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.p1_mprddlctl = 0x30322A3C,
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.p1_mpwrdlctl = 0x48304A3E,
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};
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static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
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.cs_density = 16,
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.cs1_mirror = 1,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 1,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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};
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static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
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.mem_speed = 1066,
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.density = 4,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1324,
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.trcmin = 59500,
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.trasmin = 9750,
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.SRT = 0,
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};
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static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
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{
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if (reset)
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((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
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cm_fx6_ddr3_cfg_q.rowaddr = 14;
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switch (dram_config) {
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case DDR_16BIT_256MB:
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cm_fx6_sysinfo_q.dsize = 0;
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cm_fx6_sysinfo_q.ncs = 1;
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break;
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case DDR_32BIT_512MB:
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cm_fx6_sysinfo_q.dsize = 1;
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cm_fx6_sysinfo_q.ncs = 1;
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break;
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case DDR_64BIT_1GB:
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cm_fx6_sysinfo_q.dsize = 2;
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cm_fx6_sysinfo_q.ncs = 1;
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break;
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case DDR_64BIT_2GB:
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cm_fx6_sysinfo_q.dsize = 2;
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cm_fx6_sysinfo_q.ncs = 2;
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break;
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case DDR_64BIT_4GB:
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cm_fx6_sysinfo_q.dsize = 2;
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cm_fx6_sysinfo_q.ncs = 2;
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cm_fx6_ddr3_cfg_q.rowaddr = 15;
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break;
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default:
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puts("Tried to setup invalid DDR configuration\n");
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hang();
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}
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mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
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udelay(100);
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}
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static int cm_fx6_spl_dram_init(void)
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{
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unsigned long bank1_size, bank2_size;
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switch (get_cpu_type()) {
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case MXC_CPU_MX6SOLO:
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mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
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spl_mx6s_dram_init(DDR_32BIT_1GB, false);
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bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
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bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
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if (bank1_size == 0x20000000) {
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if (bank2_size == 0x20000000)
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return 0;
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spl_mx6s_dram_init(DDR_32BIT_512MB, true);
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return 0;
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}
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spl_mx6s_dram_init(DDR_16BIT_256MB, true);
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bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
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if (bank1_size == 0x10000000)
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return 0;
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break;
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case MXC_CPU_MX6D:
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case MXC_CPU_MX6Q:
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mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
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spl_mx6q_dram_init(DDR_64BIT_4GB, false);
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bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
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if (bank1_size == 0x80000000)
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return 0;
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if (bank1_size == 0x40000000) {
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bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
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0x80000000);
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if (bank2_size == 0x40000000) {
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/* Don't do a full reset here */
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spl_mx6q_dram_init(DDR_64BIT_2GB, false);
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} else {
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spl_mx6q_dram_init(DDR_64BIT_1GB, true);
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}
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return 0;
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}
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spl_mx6q_dram_init(DDR_32BIT_512MB, true);
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bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
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if (bank1_size == 0x20000000)
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return 0;
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spl_mx6q_dram_init(DDR_16BIT_256MB, true);
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bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
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if (bank1_size == 0x10000000)
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return 0;
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break;
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}
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return -1;
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}
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static iomux_v3_cfg_t const uart4_pads[] = {
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IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static void cm_fx6_setup_uart(void)
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{
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SETUP_IOMUX_PADS(uart4_pads);
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enable_uart_clk(1);
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}
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#ifdef CONFIG_SPL_SPI_SUPPORT
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static void cm_fx6_setup_ecspi(void)
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{
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cm_fx6_set_ecspi_iomux();
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enable_spi_clk(1, 0);
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}
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#else
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static void cm_fx6_setup_ecspi(void) { }
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#endif
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void board_init_f(ulong dummy)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/*
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* We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
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* initializes DMA very early (before all board code), so the only
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* opportunity we have to initialize APBHDMA clocks is in SPL.
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*/
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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enable_usdhc_clk(1, 2);
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arch_cpu_init();
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timer_init();
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cm_fx6_setup_ecspi();
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cm_fx6_setup_uart();
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get_clocks();
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preloader_console_init();
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gpio_direction_output(CM_FX6_GREEN_LED, 1);
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if (cm_fx6_spl_dram_init()) {
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puts("!!!ERROR!!! DRAM detection failed!!!\n");
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hang();
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}
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memset(__bss_start, 0, __bss_end - __bss_start);
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board_init_r(NULL, 0);
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = spl_boot_device();
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switch (spl_boot_list[0]) {
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case BOOT_DEVICE_SPI:
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spl_boot_list[1] = BOOT_DEVICE_MMC1;
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break;
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case BOOT_DEVICE_MMC1:
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spl_boot_list[1] = BOOT_DEVICE_SPI;
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break;
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}
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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static struct fsl_esdhc_cfg usdhc_cfg = {
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.esdhc_base = USDHC3_BASE_ADDR,
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.max_bus_width = 4,
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};
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int board_mmc_init(bd_t *bis)
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{
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cm_fx6_set_usdhc_iomux();
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usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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return fsl_esdhc_initialize(bis, &usdhc_cfg);
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}
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#endif
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