mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-27 05:23:34 +00:00
69b0634a4e
Added some routines used by all Netstal boards:
- nm_bsp.c: - nm_show_print and
- common_misc_init_r
- set_params_for_sw_install. Very specific code to handle our SW
installation procedure
- fixed_sdram.c: Common routines for HCU4 (and upcoming) MCU25 boards
to handle sdram initialization.
- nm.h: Common header
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
105 lines
2.8 KiB
C
105 lines
2.8 KiB
C
/*
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*(C) Copyright 2005-2008 Netstal Maschinen AG
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* Niklaus Giger (Niklaus.Giger@netstal.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include "nm.h"
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#if defined(DEBUG)
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void show_sdram_registers(void)
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{
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u32 value;
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printf("SDRAM Controller Registers --\n");
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mfsdram(mem_mcopt1, value);
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printf(" SDRAM0_CFG : 0x%08x\n", value);
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mfsdram(mem_status, value);
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printf(" SDRAM0_STATUS: 0x%08x\n", value);
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mfsdram(mem_mb0cf, value);
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printf(" SDRAM0_B0CR : 0x%08x\n", value);
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mfsdram(mem_mb1cf, value);
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printf(" SDRAM0_B1CR : 0x%08x\n", value);
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mfsdram(mem_sdtr1, value);
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printf(" SDRAM0_TR : 0x%08x\n", value);
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mfsdram(mem_rtr, value);
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printf(" SDRAM0_RTR : 0x%08x\n", value);
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}
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#endif
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long int fixed_hcu4_sdram (unsigned int dram_size)
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{
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#ifdef DEBUG
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printf(__FUNCTION__);
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#endif
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/* disable memory controller */
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mtsdram(mem_mcopt1, 0x00000000);
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udelay (500);
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/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
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mtsdram(mem_besra, 0xffffffff);
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/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
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mtsdram(mem_besrb, 0xffffffff);
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/* Clear SDRAM0_ECCCFG (disable ECC) */
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mtsdram(mem_ecccf, 0x00000000);
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/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
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mtsdram(mem_eccerr, 0xffffffff);
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/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
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*/
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mtsdram(mem_sdtr1, 0x008a4015);
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/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
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* and refresh timer
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*/
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switch (dram_size >> 20) {
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case 32:
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mtsdram(mem_mb0cf, 0x00062001);
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mtsdram(mem_rtr, 0x07F00000);
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break;
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case 64:
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mtsdram(mem_mb0cf, 0x00084001);
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mtsdram(mem_rtr, 0x04100000);
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break;
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case 128:
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mtsdram(mem_mb0cf, 0x000A4001);
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mtsdram(mem_rtr, 0x04100000);
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break;
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default:
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printf("Invalid memory size of %d MB given\n", dram_size >> 20);
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}
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/* Power management idle timer set to the default. */
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mtsdram(mem_pmit, 0x07c00000);
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udelay (500);
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/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
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mtsdram(mem_mcopt1, 0x90800000);
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#ifdef DEBUG
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printf("%s: done\n", __FUNCTION__);
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#endif
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return dram_size;
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}
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