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665 lines
20 KiB
C
665 lines
20 KiB
C
/*****************************************************************************
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* (C) Copyright 2003; Tundra Semiconductor Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*****************************************************************************/
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/*----------------------------------------------------------------------------
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* FILENAME: tsi108_init.c
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*
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* Originator: Alex Bounine
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*
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* DESCRIPTION:
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* Initialization code for the Tundra Tsi108 bridge chip
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*---------------------------------------------------------------------------*/
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#include <common.h>
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#include <74xx_7xx.h>
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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#include <tsi108.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void mpicInit (int verbose);
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/*
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* Configuration Options
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*/
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typedef struct {
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ulong upper;
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ulong lower;
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} PB2OCN_LUT_ENTRY;
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PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
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/* 0 - 7 */
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{0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
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/* 8 - 15 */
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{0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
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/* 16 - 23 */
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{0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
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/* 24 - 31 */
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{0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */
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{0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
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{0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
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{0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
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{0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
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{0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
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};
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#ifdef CFG_CLK_SPREAD
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typedef struct {
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ulong ctrl0;
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ulong ctrl1;
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} PLL_CTRL_SET;
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/*
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* Clock Generator SPLL0 initialization values
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* PLL0 configuration table for various PB_CLKO freq.
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* Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
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* Fout depends on required PB_CLKO. Based on Fref = 33 MHz
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*/
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static PLL_CTRL_SET pll0_config[8] = {
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{0x00000000, 0x00000000}, /* 0: bypass */
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{0x00000000, 0x00000000}, /* 1: reserved */
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{0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
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{0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
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{0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
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{0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
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{0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
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{0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
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};
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#endif /* CFG_CLK_SPREAD */
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/*
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* Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
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* (based on recommended Tsi108 reference clock 33MHz)
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*/
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static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
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/*
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* get_board_bus_clk ()
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*
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* returns the bus clock in Hz.
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*/
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unsigned long get_board_bus_clk (void)
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{
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ulong i;
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/* Detect PB clock freq. */
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i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
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i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
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return pb_clk_sel[i] * 1000000;
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}
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/*
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* board_early_init_f ()
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*
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* board-specific initialization executed from flash
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*/
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int board_early_init_f (void)
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{
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ulong i;
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gd->mem_clk = 0;
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i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
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CG_PWRUP_STATUS);
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i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
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switch (i) {
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case 0: /* external clock */
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printf ("Using external clock\n");
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break;
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case 1: /* system clock */
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gd->mem_clk = gd->bus_clk;
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break;
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case 4: /* 133 MHz */
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case 5: /* 166 MHz */
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case 6: /* 200 MHz */
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gd->mem_clk = pb_clk_sel[i] * 1000000;
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break;
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default:
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printf ("Invalid DDR2 clock setting\n");
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return -1;
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}
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printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
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printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
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return 0;
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}
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/*
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* board_early_init_r() - Tsi108 initialization function executed right after
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* relocation. Contains code that cannot be executed from flash.
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*/
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int board_early_init_r (void)
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{
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ulong temp, i;
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ulong reg_val;
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volatile ulong *reg_ptr;
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reg_ptr =
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(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
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for (i = 0; i < 32; i++) {
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*reg_ptr++ = 0x00000201; /* SWAP ENABLED */
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*reg_ptr++ = 0x00;
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}
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__asm__ __volatile__ ("eieio");
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__asm__ __volatile__ ("sync");
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/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
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out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
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0x80000001);
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__asm__ __volatile__ ("sync");
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/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
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* read from SDRAM)
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*/
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temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
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__asm__ __volatile__ ("sync");
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/*
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* Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
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* processor bus address space. Immediately after reset LUT and address
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* translation are disabled for this BAR. Now we have to initialize LUT
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* and switch from the BOOT mode to the normal operation mode.
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*
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* The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
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* and covers 512MB of address space. To allow larger aperture we also
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* have to relocate register window of Tsi108
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*
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* Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
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* mode.
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*
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* initialize pointer to LUT associated with PB_OCN_BAR1
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*/
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reg_ptr =
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(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
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for (i = 0; i < 32; i++) {
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*reg_ptr++ = pb2ocn_lut1[i].lower;
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*reg_ptr++ = pb2ocn_lut1[i].upper;
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}
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__asm__ __volatile__ ("sync");
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/* Base addresses for CS0, CS1, CS2, CS3 */
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
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0x00000000);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
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0x00100000);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
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0x00200000);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
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0x00300000);
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__asm__ __volatile__ ("sync");
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/* Masks for HLP banks */
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
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0xFFF00000);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
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0xFFF00000);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
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0xFFF00000);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
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0xFFF00000);
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__asm__ __volatile__ ("sync");
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/* Set CTRL0 values for banks */
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
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0x7FFC44C2);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
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0x7FFC44C0);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
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0x7FFC44C0);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
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0x7FFC44C2);
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__asm__ __volatile__ ("sync");
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/* Set banks to latched mode, enabled, and other default settings */
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
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0x7C0F2000);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
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0x7C0F2000);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
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0x7C0F2000);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
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0x7C0F2000);
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__asm__ __volatile__ ("sync");
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/*
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* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
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* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
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*/
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out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
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0xE0000011);
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__asm__ __volatile__ ("sync");
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/* Make sure that OCN_BAR2 decoder is set (to allow following
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* immediate read from SDRAM)
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*/
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temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
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__asm__ __volatile__ ("sync");
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/*
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* SRI: At this point we have enabled the HLP banks. That means we can
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* now read from the NVRAM and initialize the environment variables.
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* We will over-ride the env_init called in board_init_f
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* This is really a work-around because, the HLP bank 1
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* where NVRAM resides is not visible during board_init_f
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* (lib_ppc/board.c)
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* Alternatively, we could use the I2C EEPROM at start-up to configure
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* and enable all HLP banks and not just HLP 0 as is being done for
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* Taiga Rev. 2.
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*/
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env_init ();
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#ifndef DISABLE_PBM
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/*
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* For IBM processors we have to set Address-Only commands generated
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* by PBM that are different from ones set after reset.
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*/
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temp = get_cpu_type ();
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if ((CPU_750FX == temp) || (CPU_750GX == temp))
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out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
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0x00009955);
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#endif /* DISABLE_PBM */
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#ifdef CONFIG_PCI
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/*
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* Initialize PCI/X block
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*/
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/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
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out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
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PCI_PFAB_BAR0_UPPER, 0);
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
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0xFB000001);
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__asm__ __volatile__ ("sync");
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/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
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temp = in32(CFG_TSI108_CSR_BASE +
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TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
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temp &= ~0xFF00; /* Clear the BUS_NUM field */
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out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
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temp);
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/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
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out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
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0);
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__asm__ __volatile__ ("sync");
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/* This register is on the PCI side to interpret the address it receives
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* and maps it as a IO address.
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*/
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out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
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0xFA000001);
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__asm__ __volatile__ ("sync");
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/*
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* Map PCI/X Memory Space
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*
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* Transactions directed from OCM to PCI Memory Space are directed
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* from PB to PCI
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* unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
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* If address remapping is required the corresponding PCI_PFAB_MEM32
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* and PCI_PFAB_PFMx register groups have to be configured.
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*
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* Map the path from the PCI/X bus into the system memory
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*
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* The memory mapped window assotiated with PCI P2O_BAR2 provides
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* access to the system memory without address remapping.
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* All system memory is opened for accesses initiated by PCI/X bus
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* masters.
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*
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* Initialize LUT associated with PCI P2O_BAR2
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*
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* set pointer to LUT associated with PCI P2O_BAR2
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*/
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reg_ptr =
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(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
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#ifdef DISABLE_PBM
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/* In case when PBM is disabled (no HW supported cache snoopng on PB)
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* P2O_BAR2 is directly mapped into the system memory without address
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* translation.
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*/
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reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
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for (i = 0; i < 32; i++) {
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*reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
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*reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
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}
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/* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
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reg_val = 0x00007500;
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#else
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reg_val = 0x00000002; /* Destination port = PBM */
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for (i = 0; i < 32; i++) {
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*reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
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/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
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*reg_ptr++ = 0x40000000;
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/* offset = 16MB, address translation is enabled to allow byte swapping */
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reg_val += 0x01000000;
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}
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/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
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reg_val = 0x00007100;
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#endif
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__asm__ __volatile__ ("eieio");
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__asm__ __volatile__ ("sync");
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out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
|
|
reg_val);
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
/* Set 64-bit PCI bus address for system memory
|
|
* ( 0 is the best choice for easy mapping)
|
|
*/
|
|
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
|
|
0x00000000);
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
|
|
0x00000000);
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
#ifndef DISABLE_PBM
|
|
/*
|
|
* The memory mapped window assotiated with PCI P2O_BAR3 provides
|
|
* access to the system memory using SDRAM OCN port and address
|
|
* translation. This is alternative way to access SDRAM from PCI
|
|
* required for Tsi108 emulation testing.
|
|
* All system memory is opened for accesses initiated by
|
|
* PCI/X bus masters.
|
|
*
|
|
* Initialize LUT associated with PCI P2O_BAR3
|
|
*
|
|
* set pointer to LUT associated with PCI P2O_BAR3
|
|
*/
|
|
reg_ptr =
|
|
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
|
|
|
|
reg_val = 0x00000004; /* Destination port = SDC */
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
*reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
|
|
|
|
/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
|
|
*reg_ptr++ = 0;
|
|
|
|
/* offset = 16MB, address translation is enabled to allow byte swapping */
|
|
reg_val += 0x01000000;
|
|
}
|
|
|
|
__asm__ __volatile__ ("eieio");
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
|
|
|
|
reg_val =
|
|
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
|
|
PCI_P2O_PAGE_SIZES);
|
|
reg_val &= ~0x00FF;
|
|
reg_val |= 0x0071;
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
|
|
reg_val);
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
/* Set 64-bit base PCI bus address for window (0x20000000) */
|
|
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
|
|
0x00000000);
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
|
|
0x20000000);
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
#endif /* !DISABLE_PBM */
|
|
|
|
#ifdef ENABLE_PCI_CSR_BAR
|
|
/* open if required access to Tsi108 CSRs from the PCI/X bus */
|
|
/* enable BAR0 on the PCI/X bus */
|
|
reg_val = in32(CFG_TSI108_CSR_BASE +
|
|
TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
|
|
reg_val |= 0x02;
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
|
|
reg_val);
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
|
|
0x00000000);
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
|
|
CFG_TSI108_CSR_BASE);
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Finally enable PCI/X Bus Master and Memory Space access
|
|
*/
|
|
|
|
reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
|
|
reg_val |= 0x06;
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
/*
|
|
* Initialize MPIC outputs (interrupt pins):
|
|
* Interrupt routing on the Grendel Emul. Board:
|
|
* PB_INT[0] -> INT (CPU0)
|
|
* PB_INT[1] -> INT (CPU1)
|
|
* PB_INT[2] -> MCP (CPU0)
|
|
* PB_INT[3] -> MCP (CPU1)
|
|
* Set interrupt controller outputs as Level_Sensitive/Active_Low
|
|
*/
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
/*
|
|
* Ensure that Machine Check exception is enabled
|
|
* We need it to support PCI Bus probing (configuration reads)
|
|
*/
|
|
|
|
reg_val = mfmsr ();
|
|
mtmsr(reg_val | MSR_ME);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Needed to print out L2 cache info
|
|
* used in the misc_init_r function
|
|
*/
|
|
|
|
unsigned long get_l2cr (void)
|
|
{
|
|
unsigned long l2controlreg;
|
|
asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
|
|
return l2controlreg;
|
|
}
|
|
|
|
/*
|
|
* misc_init_r()
|
|
*
|
|
* various things to do after relocation
|
|
*
|
|
*/
|
|
|
|
int misc_init_r (void)
|
|
{
|
|
#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
|
|
ulong i;
|
|
|
|
/* Ensure that Spread-Spectrum is disabled */
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
|
|
|
|
/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
|
|
* Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
|
|
*/
|
|
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
|
|
0x002e0044); /* D = 0.25% */
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
|
|
0x00000039); /* BWADJ */
|
|
|
|
/* Initialize PLL0: CG_PB_CLKO */
|
|
/* Detect PB clock freq. */
|
|
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
|
|
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
|
|
|
|
out32 (CFG_TSI108_CSR_BASE +
|
|
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
|
|
out32 (CFG_TSI108_CSR_BASE +
|
|
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
|
|
|
|
/* Wait and set SSEN for both PLL0 and 1 */
|
|
udelay (1000);
|
|
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
|
|
0x802e0044); /* D=0.25% */
|
|
out32 (CFG_TSI108_CSR_BASE +
|
|
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
|
|
0x80000000 | pll0_config[i].ctrl0);
|
|
#endif /* CFG_CLK_SPREAD */
|
|
|
|
#ifdef CFG_L2
|
|
l2cache_enable ();
|
|
#endif
|
|
printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
|
|
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
|
|
|
|
/*
|
|
* All the information needed to print the cache details is avaiblable
|
|
* at this point i.e. above call to l2cache_enable is the very last
|
|
* thing done with regards to enabling diabling the cache.
|
|
* So this seems like a good place to print all this information
|
|
*/
|
|
|
|
printf ("CACHE: ");
|
|
switch (get_cpu_type()) {
|
|
case CPU_7447A:
|
|
printf ("L1 Instruction cache - 32KB 8-way");
|
|
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
|
|
printf (" DISABLED\n");
|
|
printf ("L1 Data cache - 32KB 8-way");
|
|
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
|
|
printf (" DISABLED\n");
|
|
printf ("Unified L2 cache - 512KB 8-way");
|
|
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
|
|
printf (" DISABLED\n");
|
|
printf ("\n");
|
|
break;
|
|
|
|
case CPU_7448:
|
|
printf ("L1 Instruction cache - 32KB 8-way");
|
|
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
|
|
printf (" DISABLED\n");
|
|
printf ("L1 Data cache - 32KB 8-way");
|
|
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
|
|
printf (" DISABLED\n");
|
|
printf ("Unified L2 cache - 1MB 8-way");
|
|
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
|
|
printf (" DISABLED\n");
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|