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https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
74de7aefd7
According to the doc/feature-removal-schedule.txt, the "autoscr"
command will be replaced by the "source" command in approximately 6
months from now.
This patch prepares this change and starts a 6 month transition
period as follows:
- The new "source" command has been added, which implements exactly
the same functionlaity as the old "autoscr" command before
- The old "autoscr" command name is kept as an alias for compatibility
- Command sequences, script files atc. have been adapted to use the
new "source" command
- Related environment variables ("autoscript", "autoscript_uname")
have *not* been adapted yet; these will be renamed resp. removed in
a separate patch when the support for the "autoscr" command get's
finally dropped.
Signed-off-by: Wolfgang Denk <wd@denx.de>
248 lines
9 KiB
C
248 lines
9 KiB
C
/*
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Stuff still to be dealt with -
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*/
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#define CONFIG_RTC_MC146818
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define DEBUG_PARSER
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#define CONFIG_X86 1 /* Intel X86 CPU */
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#define CONFIG_SYS_SC520 1 /* AMD SC520 */
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#define CONFIG_SYS_SC520_SSI
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#define CONFIG_SHOW_BOOT_PROGRESS 1
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#define CONFIG_LAST_STAGE_INIT 1
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/*
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* If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
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* bottom (processor) board MUST be removed!
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*/
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#undef CONFIG_WATCHDOG
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#undef CONFIG_HW_WATCHDOG
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/*-----------------------------------------------------------------------
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* Video Configuration
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*/
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#undef CONFIG_VIDEO /* No Video Hardware */
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#undef CONFIG_CFB_CONSOLE
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024)
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#define CONFIG_BAUDRATE 9600
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/*-----------------------------------------------------------------------
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BDI /* bdinfo */
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#define CONFIG_CMD_BOOTD /* bootd */
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#define CONFIG_CMD_CONSOLE /* coninfo */
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#define CONFIG_CMD_ECHO /* echo arguments */
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#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
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#define CONFIG_CMD_FPGA /* FPGA configuration Support */
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#define CONFIG_CMD_IMI /* iminfo */
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#define CONFIG_CMD_IMLS /* List all found images */
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#define CONFIG_CMD_IRQ /* IRQ Information */
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#define CONFIG_CMD_ITEST /* Integer (and string) test */
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#define CONFIG_CMD_LOADB /* loadb */
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#define CONFIG_CMD_LOADS /* loads */
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#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
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#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
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#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
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#undef CONFIG_CMD_NFS /* NFS support */
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#define CONFIG_CMD_RUN /* run command in env variable */
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#define CONFIG_CMD_SAVEENV /* saveenv */
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#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
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#define CONFIG_CMD_SOURCE /* "source" command Support */
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#define CONFIG_CMD_XIMG /* Load part of Multi Image */
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#define CONFIG_BOOTDELAY 15
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
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/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + \
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16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*-----------------------------------------------------------------------
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* SDRAM Configuration
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*/
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#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
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#define CONFIG_NR_DRAM_BANKS 4
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/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
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#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
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#undef CONFIG_SYS_SDRAM_REFRESH_RATE
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#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
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#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
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#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
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/*-----------------------------------------------------------------------
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* CPU Features
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*/
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#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
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#undef CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */
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#define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */
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#undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */
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#undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */
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#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
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* in the SC520 on the CDP */
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#define CONFIG_SYS_PCAT_INTERRUPTS
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#define CONFIG_SYS_NUM_IRQS 16
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/*-----------------------------------------------------------------------
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* Memory organization
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*/
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#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
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#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
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#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
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#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
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#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/*-----------------------------------------------------------------------
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* FLASH configuration
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*/
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#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
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#define CONFIG_FLASH_CFI_LEGACY
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#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
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#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE_1, \
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CONFIG_SYS_FLASH_BASE_2}
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CONFIG_SYS_FLASH_LEGACY_512Kx8
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/*-----------------------------------------------------------------------
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* Environment configuration
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE_1 + \
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CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* PCI configuration
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*/
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#undef CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP /* pci plug-and-play */
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#undef CONFIG_PCI_SCAN_SHOW
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#undef CONFIG_SYS_FIRST_PCI_IRQ
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#undef CONFIG_SYS_SECOND_PCI_IRQ
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#undef CONFIG_SYS_THIRD_PCI_IRQ
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#undef CONFIG_SYS_FORTH_PCI_IRQ
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/*-----------------------------------------------------------------------
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* Hardware watchdog configuration
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*/
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#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000
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#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0
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#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0
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#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0
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/*-----------------------------------------------------------------------
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* FPGA configuration
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*/
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#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
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#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
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#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
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#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
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#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
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#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
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#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
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#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
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#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
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#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
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#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
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#ifndef __ASSEMBLER__
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extern unsigned long ip;
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#define PRINTIP asm ("call next_line\n" \
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"next_line:\n" \
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"pop %%eax\n" \
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"movl %%eax, %0\n" \
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:"=r"(ip) \
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: /* No Input Registers */ \
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:"%eax"); \
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printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
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#endif
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#endif /* __CONFIG_H */
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