mirror of
https://github.com/AsahiLinux/u-boot
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ae3527f088
We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
210 lines
5 KiB
C
210 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016-17 Microsemi Corporation.
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* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
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*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*
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* Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
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*/
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#include <linux/compat.h>
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#include <common.h>
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#include <efi_loader.h>
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#include <hang.h>
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#include <irq_func.h>
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#include <asm/global_data.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/encoding.h>
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#include <semihosting.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void show_efi_loaded_images(uintptr_t epc)
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{
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efi_print_image_infos((void *)epc);
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}
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static void show_regs(struct pt_regs *regs)
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{
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#ifdef CONFIG_SHOW_REGS
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printf("\nSP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n",
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regs->sp, regs->gp, regs->tp);
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printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n",
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regs->t0, regs->t1, regs->t2);
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printf("S0: " REG_FMT " S1: " REG_FMT " A0: " REG_FMT "\n",
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regs->s0, regs->s1, regs->a0);
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printf("A1: " REG_FMT " A2: " REG_FMT " A3: " REG_FMT "\n",
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regs->a1, regs->a2, regs->a3);
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printf("A4: " REG_FMT " A5: " REG_FMT " A6: " REG_FMT "\n",
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regs->a4, regs->a5, regs->a6);
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printf("A7: " REG_FMT " S2: " REG_FMT " S3: " REG_FMT "\n",
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regs->a7, regs->s2, regs->s3);
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printf("S4: " REG_FMT " S5: " REG_FMT " S6: " REG_FMT "\n",
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regs->s4, regs->s5, regs->s6);
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printf("S7: " REG_FMT " S8: " REG_FMT " S9: " REG_FMT "\n",
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regs->s7, regs->s8, regs->s9);
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printf("S10: " REG_FMT " S11: " REG_FMT " T3: " REG_FMT "\n",
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regs->s10, regs->s11, regs->t3);
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printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n",
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regs->t4, regs->t5, regs->t6);
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#endif
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}
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/**
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* instr_len() - get instruction length
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*
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* @i: low 16 bits of the instruction
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* Return: number of u16 in instruction
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*/
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static int instr_len(u16 i)
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{
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if ((i & 0x03) != 0x03)
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return 1;
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/* Instructions with more than 32 bits are not yet specified */
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return 2;
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}
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/**
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* show_code() - display code leading to exception
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*
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* @epc: program counter
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*/
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static void show_code(ulong epc)
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{
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u16 *pos = (u16 *)(epc & ~1UL);
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int i, len = instr_len(*pos);
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printf("\nCode: ");
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for (i = -8; i; ++i)
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printf("%04x ", pos[i]);
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printf("(");
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for (i = 0; i < len; ++i)
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printf("%04x%s", pos[i], i + 1 == len ? ")\n" : " ");
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}
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static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
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{
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static const char * const exception_code[] = {
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"Instruction address misaligned",
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"Instruction access fault",
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"Illegal instruction",
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"Breakpoint",
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"Load address misaligned",
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"Load access fault",
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"Store/AMO address misaligned",
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"Store/AMO access fault",
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"Environment call from U-mode",
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"Environment call from S-mode",
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"Reserved",
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"Environment call from M-mode",
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"Instruction page fault",
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"Load page fault",
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"Reserved",
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"Store/AMO page fault",
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};
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if (code < ARRAY_SIZE(exception_code))
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printf("Unhandled exception: %s\n", exception_code[code]);
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else
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printf("Unhandled exception code: %ld\n", code);
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printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n",
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epc, regs->ra, tval);
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/* Print relocation adjustments, but only if gd is initialized */
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if (gd && gd->flags & GD_FLG_RELOC)
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printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n",
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epc - gd->reloc_off, regs->ra - gd->reloc_off);
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show_regs(regs);
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show_code(epc);
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show_efi_loaded_images(epc);
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panic("\n");
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}
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int interrupt_init(void)
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{
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return 0;
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}
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/*
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* enable interrupts
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*/
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void enable_interrupts(void)
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{
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}
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/*
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* disable interrupts
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*/
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int disable_interrupts(void)
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{
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return 0;
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}
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ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
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{
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ulong is_irq, irq;
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/* An UEFI application may have changed gd. Restore U-Boot's gd. */
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efi_restore_gd();
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if (cause == CAUSE_BREAKPOINT &&
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CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)) {
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ulong pre_addr = epc - 4, post_addr = epc + 4;
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/* Check for prior and post addresses to be in same page. */
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if ((pre_addr & ~(PAGE_SIZE - 1)) ==
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(post_addr & ~(PAGE_SIZE - 1))) {
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u32 pre = *(u32 *)pre_addr;
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u32 post = *(u32 *)post_addr;
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/* Check for semihosting, i.e.:
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* slli zero,zero,0x1f
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* ebreak
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* srai zero,zero,0x7
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*/
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if (pre == 0x01f01013 && post == 0x40705013) {
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disable_semihosting();
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epc += 4;
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return epc;
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}
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}
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}
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is_irq = (cause & MCAUSE_INT);
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irq = (cause & ~MCAUSE_INT);
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if (is_irq) {
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switch (irq) {
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case IRQ_M_EXT:
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case IRQ_S_EXT:
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external_interrupt(0); /* handle external interrupt */
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break;
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case IRQ_M_TIMER:
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case IRQ_S_TIMER:
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timer_interrupt(0); /* handle timer interrupt */
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break;
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default:
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_exit_trap(cause, epc, tval, regs);
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break;
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};
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} else {
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_exit_trap(cause, epc, tval, regs);
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}
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return epc;
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}
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/*
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*Entry Point for PLIC Interrupt Handler
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*/
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__attribute__((weak)) void external_interrupt(struct pt_regs *regs)
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{
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}
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__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
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{
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}
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