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https://github.com/AsahiLinux/u-boot
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ea1af9f26b
On sun9i, the GTBUS manages transaction priority and bandwidth for multiple read ports when accessing DRAM. The initialisation mirrors the settings from Allwinner's boot0 for now, even though this may not be optimal for all applications (e.g. headless systems might want to give priority to IO modules). Adding a common callout to gtbus_init() from the SPL clock init with a weakly defined implementation in sunxi/clock.c to fallback to for platforms that don't require this. [wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
92 lines
2.5 KiB
C
92 lines
2.5 KiB
C
/*
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* GTBUS initialisation for sun9i
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*
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* (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
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* Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_GTBUS_SUN9I_H
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#define _SUNXI_GTBUS_SUN9I_H
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#include <linux/types.h>
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struct sunxi_gtbus_reg {
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u32 mst_cfg[36]; /* 0x000 */
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u8 reserved1[0x70]; /* 0x090 */
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u32 bw_wdw_cfg; /* 0x100 */
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u32 mst_read_prio_cfg[2]; /* 0x104 */
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u32 lvl2_mst_cfg; /* 0x10c */
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u32 sw_clk_on; /* 0x110 */
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u32 sw_clk_off; /* 0x114 */
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u32 pmu_mst_en; /* 0x118 */
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u32 pmu_cfg; /* 0x11c */
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u32 pmu_cnt[19]; /* 0x120 */
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u32 reserved2[0x94]; /* 0x16c */
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u32 cci400_config[3]; /* 0x200 */
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u32 cci400_status[2]; /* 0x20c */
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};
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/* for register GT_MST_CFG_REG(n) */
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#define GT_ENABLE_REQ (1<<31) /* clock on */
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#define GT_DISABLE_REQ (1<<30) /* clock off */
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#define GT_QOS_SHIFT 28
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#define GT_THD1_SHIFT 16
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#define GT_REQN_MAX 0xf /* max no master requests in one cycle */
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#define GT_REQN_SHIFT 12
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#define GT_THD0_SHIFT 0
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#define GT_QOS_MAX 0x3
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#define GT_THD_MAX 0xfff
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#define GT_BW_WDW_MAX 0xffff
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/* mst_read_prio_cfg */
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#define GT_PRIO_LOW 0
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#define GT_PRIO_HIGH 1
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/* GTBUS port ids */
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#define GT_PORT_CPUM1 0
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#define GT_PORT_CPUM2 1
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#define GT_PORT_SATA 2
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#define GT_PORT_USB3 3
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#define GT_PORT_FE0 4
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#define GT_PORT_BE1 5
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#define GT_PORT_BE2 6
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#define GT_PORT_IEP0 7
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#define GT_PORT_FE1 8
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#define GT_PORT_BE0 9
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#define GT_PORT_FE2 10
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#define GT_PORT_IEP1 11
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#define GT_PORT_VED 12
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#define GT_PORT_VEE 13
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#define GT_PORT_FD 14
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#define GT_PORT_CSI 15
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#define GT_PORT_MP 16
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#define GT_PORT_HSI 17
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#define GT_PORT_SS 18
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#define GT_PORT_TS 19
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#define GT_PORT_DMA 20
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#define GT_PORT_NDFC0 21
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#define GT_PORT_NDFC1 22
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#define GT_PORT_CPUS 23
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#define GT_PORT_TH 24
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#define GT_PORT_GMAC 25
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#define GT_PORT_USB0 26
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#define GT_PORT_MSTG0 27
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#define GT_PORT_MSTG1 28
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#define GT_PORT_MSTG2 29
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#define GT_PORT_MSTG3 30
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#define GT_PORT_USB1 31
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#define GT_PORT_GPU0 32
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#define GT_PORT_GPU1 33
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#define GT_PORT_USB2 34
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#define GT_PORT_CPUM0 35
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#define GP_MST_CFG_DEFAULT \
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((GT_QOS_MAX << GT_QOS_SHIFT) | \
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(GT_THD_MAX << GT_THD1_SHIFT) | \
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(GT_REQN_MAX << GT_REQN_SHIFT) | \
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(GT_THD_MAX << GT_THD0_SHIFT))
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#endif
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