mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
461 lines
14 KiB
C
461 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* HW data initialization for OMAP4
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*
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* (C) Copyright 2013
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* Texas Instruments, <www.ti.com>
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*
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* Sricharan R <r.sricharan@ti.com>
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*/
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#include <common.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/omap_common.h>
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#include <asm/arch/clock.h>
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#include <asm/omap_gpio.h>
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#include <asm/io.h>
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struct prcm_regs const **prcm =
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(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
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struct dplls const **dplls_data =
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(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
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struct vcores_data const **omap_vcores =
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(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
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struct omap_sys_ctrl_regs const **ctrl =
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(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
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/*
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* The M & N values in the following tables are created using the
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* following tool:
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* tools/omap/clocks_get_m_n.c
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* Please use this tool for creating the table for any new frequency.
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*/
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/*
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* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
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* OMAP4460 OPP_NOM frequency
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*/
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static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
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{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/*
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* dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
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* OMAP4430 OPP_TURBO frequency
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* OMAP4470 OPP_NOM frequency
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*/
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static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/*
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* dpll locked at 1200 MHz - MPU clk at 600 MHz
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* OMAP4430 OPP_NOM frequency
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*/
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static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
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{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* OMAP4460 OPP_NOM frequency */
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/* OMAP4470 OPP_NOM (Low Power) frequency */
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static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
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{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* OMAP4430 ES1 OPP_NOM frequency */
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static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
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{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
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{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
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{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* OMAP4430 ES2.X OPP_NOM frequency */
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static const struct dpll_params
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core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
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{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
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{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
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{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
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{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
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{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
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{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
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{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
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{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
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{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
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{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
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{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
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{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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/* ABE M & N values with sys_clk as source */
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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static const struct dpll_params
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abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
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{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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#else
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/* ABE M & N values with 32K clock as source */
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static const struct dpll_params abe_dpll_params_32k_196608khz = {
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750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
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};
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#endif
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static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
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{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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struct dplls omap4430_dplls_es1 = {
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.mpu = mpu_dpll_params_1200mhz,
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.core = core_dpll_params_es1_1524mhz,
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.per = per_dpll_params_1536mhz,
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.iva = iva_dpll_params_1862mhz,
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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.abe = abe_dpll_params_sysclk_196608khz,
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#else
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.abe = &abe_dpll_params_32k_196608khz,
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#endif
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.usb = usb_dpll_params_1920mhz,
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.ddr = NULL
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};
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struct dplls omap4430_dplls_es20 = {
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.mpu = mpu_dpll_params_1200mhz,
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.core = core_dpll_params_es2_1600mhz_ddr200mhz,
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.per = per_dpll_params_1536mhz,
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.iva = iva_dpll_params_1862mhz,
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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.abe = abe_dpll_params_sysclk_196608khz,
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#else
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.abe = &abe_dpll_params_32k_196608khz,
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#endif
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.usb = usb_dpll_params_1920mhz,
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.ddr = NULL
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};
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struct dplls omap4430_dplls = {
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.mpu = mpu_dpll_params_1200mhz,
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.core = core_dpll_params_1600mhz,
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.per = per_dpll_params_1536mhz,
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.iva = iva_dpll_params_1862mhz,
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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.abe = abe_dpll_params_sysclk_196608khz,
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#else
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.abe = &abe_dpll_params_32k_196608khz,
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#endif
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.usb = usb_dpll_params_1920mhz,
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.ddr = NULL
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};
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struct dplls omap4460_dplls = {
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.mpu = mpu_dpll_params_1400mhz,
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.core = core_dpll_params_1600mhz,
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.per = per_dpll_params_1536mhz,
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.iva = iva_dpll_params_1862mhz,
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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.abe = abe_dpll_params_sysclk_196608khz,
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#else
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.abe = &abe_dpll_params_32k_196608khz,
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#endif
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.usb = usb_dpll_params_1920mhz,
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.ddr = NULL
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};
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struct dplls omap4470_dplls = {
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.mpu = mpu_dpll_params_1600mhz,
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.core = core_dpll_params_1600mhz,
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.per = per_dpll_params_1536mhz,
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.iva = iva_dpll_params_1862mhz,
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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.abe = abe_dpll_params_sysclk_196608khz,
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#else
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.abe = &abe_dpll_params_32k_196608khz,
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#endif
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.usb = usb_dpll_params_1920mhz,
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.ddr = NULL
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};
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struct pmic_data twl6030_4430es1 = {
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.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
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.step = 12660, /* 12.66 mV represented in uV */
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/* The code starts at 1 not 0 */
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.start_code = 1,
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.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
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.pmic_bus_init = sri2c_init,
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.pmic_write = omap_vc_bypass_send_value,
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};
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/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
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struct pmic_data twl6030 = {
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.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
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.step = 12660, /* 12.66 mV represented in uV */
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/* The code starts at 1 not 0 */
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.start_code = 1,
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.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
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.pmic_bus_init = sri2c_init,
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.pmic_write = omap_vc_bypass_send_value,
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};
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struct pmic_data tps62361 = {
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.base_offset = TPS62361_BASE_VOLT_MV,
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.step = 10000, /* 10 mV represented in uV */
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.start_code = 0,
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.gpio = TPS62361_VSEL0_GPIO,
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.gpio_en = 1,
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.i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
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.pmic_bus_init = sri2c_init,
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.pmic_write = omap_vc_bypass_send_value,
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};
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struct vcores_data omap4430_volts_es1 = {
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.mpu.value[OPP_NOM] = 1325,
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.mpu.addr = SMPS_REG_ADDR_VCORE1,
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.mpu.pmic = &twl6030_4430es1,
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.core.value[OPP_NOM] = 1200,
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.core.addr = SMPS_REG_ADDR_VCORE3,
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.core.pmic = &twl6030_4430es1,
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.mm.value[OPP_NOM] = 1200,
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.mm.addr = SMPS_REG_ADDR_VCORE2,
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.mm.pmic = &twl6030_4430es1,
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};
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struct vcores_data omap4430_volts = {
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.mpu.value[OPP_NOM] = 1325,
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.mpu.addr = SMPS_REG_ADDR_VCORE1,
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.mpu.pmic = &twl6030,
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.core.value[OPP_NOM] = 1200,
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.core.addr = SMPS_REG_ADDR_VCORE3,
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.core.pmic = &twl6030,
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.mm.value[OPP_NOM] = 1200,
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.mm.addr = SMPS_REG_ADDR_VCORE2,
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.mm.pmic = &twl6030,
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};
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struct vcores_data omap4460_volts = {
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.mpu.value[OPP_NOM] = 1203,
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.mpu.addr = TPS62361_REG_ADDR_SET1,
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.mpu.pmic = &tps62361,
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.core.value[OPP_NOM] = 1200,
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.core.addr = SMPS_REG_ADDR_VCORE1,
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.core.pmic = &twl6030,
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.mm.value[OPP_NOM] = 1200,
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.mm.addr = SMPS_REG_ADDR_VCORE2,
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.mm.pmic = &twl6030,
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};
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/*
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* Take closest integer part of the mV value corresponding to a TWL6032 SMPS
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* voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
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*/
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struct vcores_data omap4470_volts = {
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.mpu.value[OPP_NOM] = 1202,
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.mpu.addr = SMPS_REG_ADDR_SMPS1,
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.mpu.pmic = &twl6030,
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.core.value[OPP_NOM] = 1126,
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.core.addr = SMPS_REG_ADDR_SMPS2,
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.core.pmic = &twl6030,
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.mm.value[OPP_NOM] = 1139,
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.mm.addr = SMPS_REG_ADDR_SMPS5,
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.mm.pmic = &twl6030,
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};
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/*
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* Enable essential clock domains, modules and
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* do some additional special settings needed
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*/
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void enable_basic_clocks(void)
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{
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u32 const clk_domains_essential[] = {
|
|
(*prcm)->cm_l4per_clkstctrl,
|
|
(*prcm)->cm_l3init_clkstctrl,
|
|
(*prcm)->cm_memif_clkstctrl,
|
|
(*prcm)->cm_l4cfg_clkstctrl,
|
|
0
|
|
};
|
|
|
|
u32 const clk_modules_hw_auto_essential[] = {
|
|
(*prcm)->cm_l3_gpmc_clkctrl,
|
|
(*prcm)->cm_memif_emif_1_clkctrl,
|
|
(*prcm)->cm_memif_emif_2_clkctrl,
|
|
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
|
|
(*prcm)->cm_wkup_gpio1_clkctrl,
|
|
(*prcm)->cm_l4per_gpio2_clkctrl,
|
|
(*prcm)->cm_l4per_gpio3_clkctrl,
|
|
(*prcm)->cm_l4per_gpio4_clkctrl,
|
|
(*prcm)->cm_l4per_gpio5_clkctrl,
|
|
(*prcm)->cm_l4per_gpio6_clkctrl,
|
|
0
|
|
};
|
|
|
|
u32 const clk_modules_explicit_en_essential[] = {
|
|
(*prcm)->cm_wkup_gptimer1_clkctrl,
|
|
(*prcm)->cm_l3init_hsmmc1_clkctrl,
|
|
(*prcm)->cm_l3init_hsmmc2_clkctrl,
|
|
(*prcm)->cm_l4per_gptimer2_clkctrl,
|
|
(*prcm)->cm_wkup_wdtimer2_clkctrl,
|
|
(*prcm)->cm_l4per_uart3_clkctrl,
|
|
(*prcm)->cm_l4per_i2c1_clkctrl,
|
|
(*prcm)->cm_l4per_i2c2_clkctrl,
|
|
(*prcm)->cm_l4per_i2c3_clkctrl,
|
|
(*prcm)->cm_l4per_i2c4_clkctrl,
|
|
0
|
|
};
|
|
|
|
/* Enable optional additional functional clock for GPIO4 */
|
|
setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
|
|
GPIO4_CLKCTRL_OPTFCLKEN_MASK);
|
|
|
|
/* Enable 96 MHz clock for MMC1 & MMC2 */
|
|
setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
|
|
HSMMC_CLKCTRL_CLKSEL_MASK);
|
|
setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
|
|
HSMMC_CLKCTRL_CLKSEL_MASK);
|
|
|
|
/* Select 32KHz clock as the source of GPTIMER1 */
|
|
setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
|
|
GPTIMER1_CLKCTRL_CLKSEL_MASK);
|
|
|
|
/* Enable optional 48M functional clock for USB PHY */
|
|
setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
|
|
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
|
|
|
|
/* Enable 32 KHz clock for USB PHY */
|
|
setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
|
|
USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
|
|
|
|
do_enable_clocks(clk_domains_essential,
|
|
clk_modules_hw_auto_essential,
|
|
clk_modules_explicit_en_essential,
|
|
1);
|
|
}
|
|
|
|
void enable_basic_uboot_clocks(void)
|
|
{
|
|
u32 const clk_domains_essential[] = {
|
|
0
|
|
};
|
|
|
|
u32 const clk_modules_hw_auto_essential[] = {
|
|
(*prcm)->cm_l3init_hsusbotg_clkctrl,
|
|
(*prcm)->cm_l3init_usbphy_clkctrl,
|
|
(*prcm)->cm_clksel_usb_60mhz,
|
|
(*prcm)->cm_l3init_hsusbtll_clkctrl,
|
|
0
|
|
};
|
|
|
|
u32 const clk_modules_explicit_en_essential[] = {
|
|
(*prcm)->cm_l4per_mcspi1_clkctrl,
|
|
(*prcm)->cm_l3init_hsusbhost_clkctrl,
|
|
0
|
|
};
|
|
|
|
do_enable_clocks(clk_domains_essential,
|
|
clk_modules_hw_auto_essential,
|
|
clk_modules_explicit_en_essential,
|
|
1);
|
|
}
|
|
|
|
void hw_data_init(void)
|
|
{
|
|
u32 omap_rev = omap_revision();
|
|
|
|
(*prcm) = &omap4_prcm;
|
|
|
|
switch (omap_rev) {
|
|
|
|
case OMAP4430_ES1_0:
|
|
*dplls_data = &omap4430_dplls_es1;
|
|
*omap_vcores = &omap4430_volts_es1;
|
|
break;
|
|
|
|
case OMAP4430_ES2_0:
|
|
*dplls_data = &omap4430_dplls_es20;
|
|
*omap_vcores = &omap4430_volts;
|
|
break;
|
|
|
|
case OMAP4430_ES2_1:
|
|
case OMAP4430_ES2_2:
|
|
case OMAP4430_ES2_3:
|
|
*dplls_data = &omap4430_dplls;
|
|
*omap_vcores = &omap4430_volts;
|
|
break;
|
|
|
|
case OMAP4460_ES1_0:
|
|
case OMAP4460_ES1_1:
|
|
*dplls_data = &omap4460_dplls;
|
|
*omap_vcores = &omap4460_volts;
|
|
break;
|
|
|
|
case OMAP4470_ES1_0:
|
|
*dplls_data = &omap4470_dplls;
|
|
*omap_vcores = &omap4470_volts;
|
|
break;
|
|
|
|
default:
|
|
printf("\n INVALID OMAP REVISION ");
|
|
}
|
|
|
|
*ctrl = &omap4_ctrl;
|
|
}
|