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https://github.com/AsahiLinux/u-boot
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7246ec1934
SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This requires u-boot to update API implementation, since it will cause compatible issue. Otherwise all pad checking will have problem and cause pad setting not continue. Due to the compatible issue, the new u-boot only works with new SCFW (API version: 1.21 and later). old scfw + old u-boot: API overflow issue old scfw + new u-boot, or new scfw + old u-boot: API compatible issue new scfw + new u-boot: Working Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Jason Liu <Jason.hui.liu@nxp.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
230 lines
9.5 KiB
C
230 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017-2018 NXP
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*
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*/
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#ifndef SC_RPC_H
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#define SC_RPC_H
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/* Note: Check SCFW API Released DOC before you want to modify something */
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/* Defines */
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#define SCFW_API_VERSION_MAJOR 1U
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#define SCFW_API_VERSION_MINOR 21U
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#define SC_RPC_VERSION 1U
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#define SC_RPC_MAX_MSG 8U
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#define RPC_VER(MSG) ((MSG)->version)
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#define RPC_SIZE(MSG) ((MSG)->size)
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#define RPC_SVC(MSG) ((MSG)->svc)
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#define RPC_FUNC(MSG) ((MSG)->func)
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#define RPC_R8(MSG) ((MSG)->func)
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#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
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(s64)(RPC_U32((MSG), (IDX) + 4U))
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#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U])
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#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U])
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#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
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#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
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(u64)(RPC_U32((MSG), (IDX) + 4U))
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#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
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#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U])
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#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
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#define SC_RPC_SVC_UNKNOWN 0U
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#define SC_RPC_SVC_RETURN 1U
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#define SC_RPC_SVC_PM 2U
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#define SC_RPC_SVC_RM 3U
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#define SC_RPC_SVC_TIMER 5U
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#define SC_RPC_SVC_PAD 6U
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#define SC_RPC_SVC_MISC 7U
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#define SC_RPC_SVC_IRQ 8U
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#define SC_RPC_SVC_SECO 9U
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#define SC_RPC_SVC_ABORT 10U
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/* Types */
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struct sc_rpc_msg_s {
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u8 version;
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u8 size;
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u8 svc;
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u8 func;
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union {
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s32 i32[(SC_RPC_MAX_MSG - 1U)];
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s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U];
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s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U];
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u32 u32[(SC_RPC_MAX_MSG - 1U)];
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u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U];
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u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U];
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} DATA;
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};
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/* PM RPC */
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#define PM_FUNC_UNKNOWN 0
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#define PM_FUNC_SET_SYS_POWER_MODE 19U
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#define PM_FUNC_SET_PARTITION_POWER_MODE 1U
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#define PM_FUNC_GET_SYS_POWER_MODE 2U
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#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U
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#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U
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#define PM_FUNC_REQ_LOW_POWER_MODE 16U
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#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U
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#define PM_FUNC_SET_CPU_RESUME_ADDR 17U
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#define PM_FUNC_SET_CPU_RESUME 21U
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#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U
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#define PM_FUNC_SET_CLOCK_RATE 5U
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#define PM_FUNC_GET_CLOCK_RATE 6U
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#define PM_FUNC_CLOCK_ENABLE 7U
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#define PM_FUNC_SET_CLOCK_PARENT 14U
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#define PM_FUNC_GET_CLOCK_PARENT 15U
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#define PM_FUNC_RESET 13U
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#define PM_FUNC_RESET_REASON 10U
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#define PM_FUNC_BOOT 8U
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#define PM_FUNC_REBOOT 9U
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#define PM_FUNC_REBOOT_PARTITION 12U
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#define PM_FUNC_CPU_START 11U
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#define PM_FUNC_CPU_RESET 23U
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#define PM_FUNC_RESOURCE_RESET 29U
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#define PM_FUNC_IS_PARTITION_STARTED 24U
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/* MISC RPC */
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#define MISC_FUNC_UNKNOWN 0
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#define MISC_FUNC_SET_CONTROL 1U
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#define MISC_FUNC_GET_CONTROL 2U
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#define MISC_FUNC_SET_MAX_DMA_GROUP 4U
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#define MISC_FUNC_SET_DMA_GROUP 5U
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#define MISC_FUNC_SECO_IMAGE_LOAD 8U
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#define MISC_FUNC_SECO_AUTHENTICATE 9U
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#define MISC_FUNC_SECO_FUSE_WRITE 20U
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#define MISC_FUNC_SECO_ENABLE_DEBUG 21U
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#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U
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#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U
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#define MISC_FUNC_SECO_BUILD_INFO 24U
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#define MISC_FUNC_DEBUG_OUT 10U
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#define MISC_FUNC_WAVEFORM_CAPTURE 6U
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#define MISC_FUNC_BUILD_INFO 15U
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#define MISC_FUNC_UNIQUE_ID 19U
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#define MISC_FUNC_SET_ARI 3U
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#define MISC_FUNC_BOOT_STATUS 7U
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#define MISC_FUNC_BOOT_DONE 14U
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#define MISC_FUNC_OTP_FUSE_READ 11U
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#define MISC_FUNC_OTP_FUSE_WRITE 17U
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#define MISC_FUNC_SET_TEMP 12U
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#define MISC_FUNC_GET_TEMP 13U
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#define MISC_FUNC_GET_BOOT_DEV 16U
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#define MISC_FUNC_GET_BUTTON_STATUS 18U
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#define MISC_FUNC_GET_BOOT_CONTAINER 36U
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/* PAD RPC */
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#define PAD_FUNC_UNKNOWN 0
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#define PAD_FUNC_SET_MUX 1U
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#define PAD_FUNC_GET_MUX 6U
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#define PAD_FUNC_SET_GP 2U
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#define PAD_FUNC_GET_GP 7U
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#define PAD_FUNC_SET_WAKEUP 4U
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#define PAD_FUNC_GET_WAKEUP 9U
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#define PAD_FUNC_SET_ALL 5U
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#define PAD_FUNC_GET_ALL 10U
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#define PAD_FUNC_SET 15U
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#define PAD_FUNC_GET 16U
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#define PAD_FUNC_SET_GP_28FDSOI 11U
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#define PAD_FUNC_GET_GP_28FDSOI 12U
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#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U
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#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U
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#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U
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#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U
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/* RM RPC */
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#define RM_FUNC_UNKNOWN 0
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#define RM_FUNC_PARTITION_ALLOC 1U
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#define RM_FUNC_SET_CONFIDENTIAL 31U
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#define RM_FUNC_PARTITION_FREE 2U
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#define RM_FUNC_GET_DID 26U
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#define RM_FUNC_PARTITION_STATIC 3U
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#define RM_FUNC_PARTITION_LOCK 4U
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#define RM_FUNC_GET_PARTITION 5U
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#define RM_FUNC_SET_PARENT 6U
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#define RM_FUNC_MOVE_ALL 7U
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#define RM_FUNC_ASSIGN_RESOURCE 8U
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#define RM_FUNC_SET_RESOURCE_MOVABLE 9U
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#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U
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#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U
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#define RM_FUNC_SET_MASTER_SID 11U
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#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U
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#define RM_FUNC_IS_RESOURCE_OWNED 13U
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#define RM_FUNC_GET_RESOURCE_OWNER 33U
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#define RM_FUNC_IS_RESOURCE_MASTER 14U
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#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U
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#define RM_FUNC_GET_RESOURCE_INFO 16U
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#define RM_FUNC_MEMREG_ALLOC 17U
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#define RM_FUNC_MEMREG_SPLIT 29U
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#define RM_FUNC_MEMREG_FREE 18U
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#define RM_FUNC_FIND_MEMREG 30U
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#define RM_FUNC_ASSIGN_MEMREG 19U
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#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U
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#define RM_FUNC_IS_MEMREG_OWNED 21U
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#define RM_FUNC_GET_MEMREG_INFO 22U
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#define RM_FUNC_ASSIGN_PAD 23U
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#define RM_FUNC_SET_PAD_MOVABLE 24U
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#define RM_FUNC_IS_PAD_OWNED 25U
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#define RM_FUNC_DUMP 27U
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/* SECO RPC */
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#define SECO_FUNC_UNKNOWN 0 /* Unknown function */
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#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */
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#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */
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#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */
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#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */
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#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */
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#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */
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#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */
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#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */
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#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */
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#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */
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#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */
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#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */
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#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */
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#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */
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#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
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#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
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#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
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#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
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#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
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#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
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#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */
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#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */
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#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */
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#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */
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#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */
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#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */
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#define SECO_FUNC_SECVIO_DGO_CONFIG 27U /* Index for sc_seco_secvio_dgo_config() RPC call */
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/* IRQ RPC */
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#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */
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#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */
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#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */
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/* TIMER RPC */
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#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
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#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
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#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
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#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
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#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
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#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
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#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */
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#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */
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#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */
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#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */
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#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */
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#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */
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#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */
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#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */
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#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */
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#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */
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#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */
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#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */
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#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */
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#endif /* SC_RPC_H */
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