mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
66 lines
2.1 KiB
C
66 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#include <asm/io.h>
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#include <asm/arch/stv0991_creg.h>
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#include <asm/arch/stv0991_periph.h>
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#include <asm/arch/hardware.h>
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static struct stv0991_creg *const stv0991_creg = \
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(struct stv0991_creg *)CREG_BASE_ADDR;
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int stv0991_pinmux_config(int peripheral)
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{
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switch (peripheral) {
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case UART_GPIOC_30_31:
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/* SSDA/SSCL pad muxing to UART Rx/Dx */
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writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
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CFG_GPIOC_31_UART_RX,
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&stv0991_creg->mux12);
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writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
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CFG_GPIOC_30_UART_TX,
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&stv0991_creg->mux12);
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/* SSDA/SSCL pad config to push pull*/
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writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
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CFG_GPIOC_31_MODE_PP,
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&stv0991_creg->cfg_pad6);
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writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
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CFG_GPIOC_30_MODE_HIGH,
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&stv0991_creg->cfg_pad6);
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break;
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case UART_GPIOB_16_17:
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/* ethernet rx_6/7 to UART Rx/Dx */
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writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
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CFG_GPIOB_17_UART_RX,
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&stv0991_creg->mux7);
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writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
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CFG_GPIOB_16_UART_TX,
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&stv0991_creg->mux7);
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break;
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case ETH_GPIOB_10_31_C_0_4:
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writel(readl(&stv0991_creg->mux6) & 0x000000FF,
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&stv0991_creg->mux6);
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writel(0x00000000, &stv0991_creg->mux7);
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writel(0x00000000, &stv0991_creg->mux8);
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writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
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&stv0991_creg->mux9);
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/* Ethernet Voltage configuration to 1.8V*/
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writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
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ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
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writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
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ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
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break;
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case QSPI_CS_CLK_PAD:
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writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) |
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CFG_FLASH_CS_NC, &stv0991_creg->mux13);
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writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) |
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CFG_FLASH_CLK, &stv0991_creg->mux13);
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default:
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break;
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}
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return 0;
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}
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