mirror of
https://github.com/AsahiLinux/u-boot
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cc74cab86a
Introduce BSH SystemMaster (SMM) M2 board family, which consists of: imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards. Add support for imx6ulz BSH SMM M2 board: - 128 MiB DDR3 RAM - 256MiB Nand - USBOTG1 peripheral - fastboot. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
130 lines
3.1 KiB
C
130 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <cpu_func.h>
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#include <hang.h>
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6ull_pins.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <linux/libfdt.h>
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#include <spl.h>
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#include <asm/arch/mx6-ddr.h>
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static const iomux_v3_cfg_t uart4_pads[] = {
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MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
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}
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000028,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_b0ds = 0x00000028,
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.grp_ctlds = 0x00000028,
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.grp_b1ds = 0x00000028,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ddr_type = 0x000c0000,
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};
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000028,
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.dram_dqm1 = 0x00000028,
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.dram_ras = 0x00000028,
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.dram_cas = 0x00000028,
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.dram_odt0 = 0x00000028,
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.dram_odt1 = 0x00000028,
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.dram_sdba2 = 0x00000000,
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.dram_sdclk_0 = 0x00000028,
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.dram_sdqs0 = 0x00000028,
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.dram_sdqs1 = 0x00000028,
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.dram_reset = 0x000c0028,
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};
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static struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00000000,
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.p0_mpwldectrl1 = 0x00100010,
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.p0_mpdgctrl0 = 0x414c014c,
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.p0_mpdgctrl1 = 0x00000000,
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.p0_mprddlctl = 0x40403a42,
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.p0_mpwrdlctl = 0x4040342e,
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};
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static struct mx6_ddr_sysinfo ddr_sysinfo = {
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.dsize = 0,
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.cs1_mirror = 0,
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.cs_density = 32,
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.ncs = 1,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 1,
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.mif3_mode = 3,
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.rst_to_cke = 0x23, /* 33 cycles (JEDEC value for DDR3) - total of 500 us */
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.sde_to_rst = 0x10, /* 14 cycles (JEDEC value for DDR3) - total of 200 us */
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.refsel = 1,
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.refr = 3,
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 1333,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 13,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1350,
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.trcmin = 4950,
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.trasmin = 3600,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0xFFFFFFFF, &ccm->CCGR0);
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writel(0xFFFFFFFF, &ccm->CCGR1);
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writel(0xFFFFFFFF, &ccm->CCGR2);
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writel(0xFFFFFFFF, &ccm->CCGR3);
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writel(0xFFFFFFFF, &ccm->CCGR4);
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writel(0xFFFFFFFF, &ccm->CCGR5);
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writel(0xFFFFFFFF, &ccm->CCGR6);
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}
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static void imx6ul_spl_dram_cfg(void)
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{
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mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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void board_init_f(ulong dummy)
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{
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ccgr_init();
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arch_cpu_init();
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timer_init();
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setup_iomux_uart();
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preloader_console_init();
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imx6ul_spl_dram_cfg();
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}
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void reset_cpu(void)
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{
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}
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