mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 17:41:08 +00:00
6b87abe3ac
SH4 and SH4A are compatible. But some instructions are different from these. In Linux kernel, It is treated as a separate CPU, but for now, I think that there is no need to divide especially in the U-Boot. This removes CONFIG_SH4A definition from source code, SH4A is treated as SH4. And this fix white space. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
31 lines
632 B
C
31 lines
632 B
C
#ifndef __ASM_SH_CACHE_H
|
|
#define __ASM_SH_CACHE_H
|
|
|
|
#if defined(CONFIG_SH4)
|
|
|
|
int cache_control(unsigned int cmd);
|
|
|
|
#define L1_CACHE_BYTES 32
|
|
|
|
struct __large_struct { unsigned long buf[100]; };
|
|
#define __m(x) (*(struct __large_struct *)(x))
|
|
|
|
#else
|
|
|
|
/*
|
|
* 32-bytes is the largest L1 data cache line size for SH the architecture. So
|
|
* it is a safe default for DMA alignment.
|
|
*/
|
|
#define ARCH_DMA_MINALIGN 32
|
|
|
|
#endif /* CONFIG_SH4 */
|
|
|
|
/*
|
|
* Use the L1 data cache line size value for the minimum DMA buffer alignment
|
|
* on SH.
|
|
*/
|
|
#ifndef ARCH_DMA_MINALIGN
|
|
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
|
|
#endif
|
|
|
|
#endif /* __ASM_SH_CACHE_H */
|