mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 05:42:58 +00:00
f9917454d5
It is common for system reset to be available at multiple levels in modern hardware. For example, an SoC may provide a reset option, and a board may provide its own reset for reasons of security or thoroughness. It is useful to be able to model this hardware without hard-coding the behaviour in the SoC or board. Also there is a distinction sometimes between resetting just the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting power. To achieve this, add a simple system reset uclass. It allows multiple devices to provide reset functionality and provides a way to walk through them, requesting a particular reset type until is it provided. Signed-off-by: Simon Glass <sjg@chromium.org>
84 lines
2.9 KiB
Text
84 lines
2.9 KiB
Text
config CMD_CROS_EC
|
|
bool "Enable crosec command"
|
|
depends on CROS_EC
|
|
help
|
|
Enable command-line access to the Chrome OS EC (Embedded
|
|
Controller). This provides the 'crosec' command which has
|
|
a number of sub-commands for performing EC tasks such as
|
|
updating its flash, accessing a small saved context area
|
|
and talking to the I2C bus behind the EC (if there is one).
|
|
|
|
config CROS_EC
|
|
bool "Enable Chrome OS EC"
|
|
help
|
|
Enable access to the Chrome OS EC. This is a separate
|
|
microcontroller typically available on a SPI bus on Chromebooks. It
|
|
provides access to the keyboard, some internal storage and may
|
|
control access to the battery and main PMIC depending on the
|
|
device. You can use the 'crosec' command to access it.
|
|
|
|
config CROS_EC_I2C
|
|
bool "Enable Chrome OS EC I2C driver"
|
|
depends on CROS_EC
|
|
help
|
|
Enable I2C access to the Chrome OS EC. This is used on older
|
|
ARM Chromebooks such as snow and spring before the standard bus
|
|
changed to SPI. The EC will accept commands across the I2C using
|
|
a special message protocol, and provide responses.
|
|
|
|
config CROS_EC_LPC
|
|
bool "Enable Chrome OS EC LPC driver"
|
|
depends on CROS_EC
|
|
help
|
|
Enable I2C access to the Chrome OS EC. This is used on x86
|
|
Chromebooks such as link and falco. The keyboard is provided
|
|
through a legacy port interface, so on x86 machines the main
|
|
function of the EC is power and thermal management.
|
|
|
|
config CROS_EC_SANDBOX
|
|
bool "Enable Chrome OS EC sandbox driver"
|
|
depends on CROS_EC && SANDBOX
|
|
help
|
|
Enable a sandbox emulation of the Chrome OS EC. This supports
|
|
keyboard (use the -l flag to enable the LCD), verified boot context,
|
|
EC flash read/write/erase support and a few other things. It is
|
|
enough to perform a Chrome OS verified boot on sandbox.
|
|
|
|
config CROS_EC_SPI
|
|
bool "Enable Chrome OS EC SPI driver"
|
|
depends on CROS_EC
|
|
help
|
|
Enable SPI access to the Chrome OS EC. This is used on newer
|
|
ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
|
|
provides a faster and more robust interface than I2C but the bugs
|
|
are less interesting.
|
|
|
|
config CONFIG_FSL_SEC_MON
|
|
bool "Enable FSL SEC_MON Driver"
|
|
help
|
|
Freescale Security Monitor block is responsible for monitoring
|
|
system states.
|
|
Security Monitor can be transitioned on any security failures,
|
|
like software violations or hardware security violations.
|
|
|
|
config PCA9551_LED
|
|
bool "Enable PCA9551 LED driver"
|
|
help
|
|
Enable driver for PCA9551 LED controller. This controller
|
|
is connected via I2C. So I2C needs to be enabled.
|
|
|
|
config PCA9551_I2C_ADDR
|
|
hex "I2C address of PCA9551 LED controller"
|
|
depends on PCA9551_LED
|
|
default 0x60
|
|
help
|
|
The I2C address of the PCA9551 LED controller.
|
|
|
|
config RESET
|
|
bool "Enable support for reset drivers"
|
|
depends on DM
|
|
help
|
|
Enable reset drivers which can be used to reset the CPU or board.
|
|
Each driver can provide a reset method which will be called to
|
|
effect a reset. The uclass will try all available drivers when
|
|
reset_walk() is called.
|