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https://github.com/AsahiLinux/u-boot
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6b85b26e4b
Move all checks before cache flush and IOC setup. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
716 lines
19 KiB
C
716 lines
19 KiB
C
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/log2.h>
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#include <asm/arcregs.h>
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#include <asm/arc-bcr.h>
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#include <asm/cache.h>
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/*
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* [ NOTE 1 ]:
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* Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable
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* operation may result in unexpected behavior and data loss even if we flush
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* data cache right before invalidation. That may happens if we store any context
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* on stack (like we store BLINK register on stack before function call).
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* BLINK register is the register where return address is automatically saved
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* when we do function call with instructions like 'bl'.
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*
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* There is the real example:
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* We may hang in the next code as we store any BLINK register on stack in
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* invalidate_dcache_all() function.
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*
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* void flush_dcache_all() {
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* __dc_entire_op(OP_FLUSH);
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* // Other code //
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* }
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*
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* void invalidate_dcache_all() {
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* __dc_entire_op(OP_INV);
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* // Other code //
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* }
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*
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* void foo(void) {
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* flush_dcache_all();
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* invalidate_dcache_all();
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* }
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*
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* Now let's see what really happens during that code execution:
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*
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* foo()
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* |->> call flush_dcache_all
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* [return address is saved to BLINK register]
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* [push BLINK] (save to stack) ![point 1]
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* |->> call __dc_entire_op(OP_FLUSH)
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* [return address is saved to BLINK register]
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* [flush L1 D$]
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* return [jump to BLINK]
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* <<------
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* [other flush_dcache_all code]
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* [pop BLINK] (get from stack)
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* return [jump to BLINK]
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* <<------
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* |->> call invalidate_dcache_all
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* [return address is saved to BLINK register]
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* [push BLINK] (save to stack) ![point 2]
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* |->> call __dc_entire_op(OP_FLUSH)
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* [return address is saved to BLINK register]
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* [invalidate L1 D$] ![point 3]
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* // Oops!!!
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* // We lose return address from invalidate_dcache_all function:
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* // we save it to stack and invalidate L1 D$ after that!
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* return [jump to BLINK]
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* <<------
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* [other invalidate_dcache_all code]
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* [pop BLINK] (get from stack)
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* // we don't have this data in L1 dcache as we invalidated it in [point 3]
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* // so we get it from next memory level (for example DDR memory)
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* // but in the memory we have value which we save in [point 1], which
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* // is return address from flush_dcache_all function (instead of
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* // address from current invalidate_dcache_all function which we
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* // saved in [point 2] !)
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* return [jump to BLINK]
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* <<------
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* // As BLINK points to invalidate_dcache_all, we call it again and
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* // loop forever.
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*
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* Fortunately we may fix that by using flush & invalidation of D$ with a single
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* one instruction (instead of flush and invalidation instructions pair) and
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* enabling force function inline with '__attribute__((always_inline))' gcc
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* attribute to avoid any function call (and BLINK store) between cache flush
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* and disable.
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*
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*
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* [ NOTE 2 ]:
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* As of today we only support the following cache configurations on ARC.
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* Other configurations may exist in HW (for example, since version 3.0 HS
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* supports SL$ (L2 system level cache) disable) but we don't support it in SW.
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* Configuration 1:
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* ______________________
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* | |
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* | ARC CPU |
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* |______________________|
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* ___|___ ___|___
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* | | | |
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* | L1 I$ | | L1 D$ |
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* |_______| |_______|
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* on/off on/off
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* ___|______________|____
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* | |
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* | main memory |
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* |______________________|
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*
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* Configuration 2:
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* ______________________
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* | |
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* | ARC CPU |
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* |______________________|
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* ___|___ ___|___
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* | | | |
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* | L1 I$ | | L1 D$ |
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* |_______| |_______|
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* on/off on/off
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* ___|______________|____
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* | |
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* | L2 (SL$) |
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* |______________________|
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* always must be on
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* ___|______________|____
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* | |
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* | main memory |
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* |______________________|
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*
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* Configuration 3:
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* ______________________
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* | |
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* | ARC CPU |
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* |______________________|
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* ___|___ ___|___
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* | | | |
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* | L1 I$ | | L1 D$ |
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* |_______| |_______|
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* on/off must be on
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* ___|______________|____ _______
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* | | | |
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* | L2 (SL$) |-----| IOC |
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* |______________________| |_______|
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* always must be on on/off
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* ___|______________|____
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* | |
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* | main memory |
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* |______________________|
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*/
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DECLARE_GLOBAL_DATA_PTR;
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/* Bit values in IC_CTRL */
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#define IC_CTRL_CACHE_DISABLE BIT(0)
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/* Bit values in DC_CTRL */
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#define DC_CTRL_CACHE_DISABLE BIT(0)
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#define DC_CTRL_INV_MODE_FLUSH BIT(6)
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#define DC_CTRL_FLUSH_STATUS BIT(8)
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#define OP_INV BIT(0)
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#define OP_FLUSH BIT(1)
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#define OP_FLUSH_N_INV (OP_FLUSH | OP_INV)
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/* Bit val in SLC_CONTROL */
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#define SLC_CTRL_DIS 0x001
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#define SLC_CTRL_IM 0x040
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#define SLC_CTRL_BUSY 0x100
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#define SLC_CTRL_RGN_OP_INV 0x200
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#define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1))
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/*
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* We don't want to use '__always_inline' macro here as it can be redefined
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* to simple 'inline' in some cases which breaks stuff. See [ NOTE 1 ] for more
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* details about the reasons we need to use always_inline functions.
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*/
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#define inlined_cachefunc inline __attribute__((always_inline))
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static inlined_cachefunc void __ic_entire_invalidate(void);
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static inlined_cachefunc void __dc_entire_op(const int cacheop);
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static inline bool pae_exists(void)
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{
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/* TODO: should we compare mmu version from BCR and from CONFIG? */
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#if (CONFIG_ARC_MMU_VER >= 4)
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union bcr_mmu_4 mmu4;
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mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
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if (mmu4.fields.pae)
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return true;
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#endif /* (CONFIG_ARC_MMU_VER >= 4) */
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return false;
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}
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static inlined_cachefunc bool icache_exists(void)
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{
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union bcr_di_cache ibcr;
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ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
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return !!ibcr.fields.ver;
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}
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static inlined_cachefunc bool icache_enabled(void)
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{
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if (!icache_exists())
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return false;
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return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE);
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}
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static inlined_cachefunc bool dcache_exists(void)
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{
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union bcr_di_cache dbcr;
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dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
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return !!dbcr.fields.ver;
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}
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static inlined_cachefunc bool dcache_enabled(void)
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{
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if (!dcache_exists())
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return false;
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return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE);
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}
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static inlined_cachefunc bool slc_exists(void)
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{
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if (is_isa_arcv2()) {
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union bcr_generic sbcr;
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sbcr.word = read_aux_reg(ARC_BCR_SLC);
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return !!sbcr.fields.ver;
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}
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return false;
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}
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static inlined_cachefunc bool slc_data_bypass(void)
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{
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/*
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* If L1 data cache is disabled SL$ is bypassed and all load/store
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* requests are sent directly to main memory.
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*/
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return !dcache_enabled();
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}
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static inline bool ioc_exists(void)
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{
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if (is_isa_arcv2()) {
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union bcr_clust_cfg cbcr;
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cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
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return cbcr.fields.c;
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}
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return false;
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}
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static inline bool ioc_enabled(void)
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{
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/*
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* We check only CONFIG option instead of IOC HW state check as IOC
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* must be disabled by default.
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*/
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if (is_ioc_enabled())
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return ioc_exists();
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return false;
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}
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static inlined_cachefunc void __slc_entire_op(const int op)
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{
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unsigned int ctrl;
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if (!slc_exists())
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return;
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ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
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if (!(op & OP_FLUSH)) /* i.e. OP_INV */
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ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
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else
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ctrl |= SLC_CTRL_IM;
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write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
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if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
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write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
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else
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write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
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/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
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read_aux_reg(ARC_AUX_SLC_CTRL);
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/* Important to wait for flush to complete */
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while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
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}
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static void slc_upper_region_init(void)
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{
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/*
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* ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
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* only if PAE exists in current HW. So we had to check pae_exist
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* before using them.
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*/
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if (!pae_exists())
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return;
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/*
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* ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
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* as we don't use PAE40.
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*/
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write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
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write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
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}
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static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
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{
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#ifdef CONFIG_ISA_ARCV2
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unsigned int ctrl;
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unsigned long end;
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if (!slc_exists())
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return;
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/*
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* The Region Flush operation is specified by CTRL.RGN_OP[11..9]
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* - b'000 (default) is Flush,
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* - b'001 is Invalidate if CTRL.IM == 0
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* - b'001 is Flush-n-Invalidate if CTRL.IM == 1
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*/
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ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
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/* Don't rely on default value of IM bit */
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if (!(op & OP_FLUSH)) /* i.e. OP_INV */
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ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
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else
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ctrl |= SLC_CTRL_IM;
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if (op & OP_INV)
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ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
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else
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ctrl &= ~SLC_CTRL_RGN_OP_INV;
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write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
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/*
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* Lower bits are ignored, no need to clip
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* END needs to be setup before START (latter triggers the operation)
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* END can't be same as START, so add (l2_line_sz - 1) to sz
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*/
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end = paddr + sz + gd->arch.slc_line_sz - 1;
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/*
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* Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
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* are always == 0 as we don't use PAE40, so we only setup lower ones
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* (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
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*/
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write_aux_reg(ARC_AUX_SLC_RGN_END, end);
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write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
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/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
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read_aux_reg(ARC_AUX_SLC_CTRL);
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while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
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#endif /* CONFIG_ISA_ARCV2 */
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}
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static void arc_ioc_setup(void)
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{
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/* IOC Aperture start is equal to DDR start */
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unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
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/* IOC Aperture size is equal to DDR size */
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long ap_size = CONFIG_SYS_SDRAM_SIZE;
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/* Unsupported configuration. See [ NOTE 2 ] for more details. */
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if (!slc_exists())
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panic("Try to enable IOC but SLC is not present");
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/* Unsupported configuration. See [ NOTE 2 ] for more details. */
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if (!dcache_enabled())
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panic("Try to enable IOC but L1 D$ is disabled");
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if (!is_power_of_2(ap_size) || ap_size < 4096)
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panic("IOC Aperture size must be power of 2 and bigger 4Kib");
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/* IOC Aperture start must be aligned to the size of the aperture */
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if (ap_base % ap_size != 0)
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panic("IOC Aperture start must be aligned to the size of the aperture");
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flush_n_invalidate_dcache_all();
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/*
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* IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
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* so setting 0x11 implies 512M, 0x12 implies 1G...
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*/
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write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
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order_base_2(ap_size / 1024) - 2);
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write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
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write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
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write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
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}
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static void read_decode_cache_bcr_arcv2(void)
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{
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#ifdef CONFIG_ISA_ARCV2
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union bcr_slc_cfg slc_cfg;
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if (slc_exists()) {
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slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
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gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
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/*
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* We don't support configuration where L1 I$ or L1 D$ is
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* absent but SL$ exists. See [ NOTE 2 ] for more details.
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*/
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if (!icache_exists() || !dcache_exists())
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panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent");
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}
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#endif /* CONFIG_ISA_ARCV2 */
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}
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void read_decode_cache_bcr(void)
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{
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int dc_line_sz = 0, ic_line_sz = 0;
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union bcr_di_cache ibcr, dbcr;
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ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
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if (ibcr.fields.ver) {
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gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
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if (!ic_line_sz)
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panic("Instruction exists but line length is 0\n");
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}
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dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
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if (dbcr.fields.ver) {
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gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
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if (!dc_line_sz)
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panic("Data cache exists but line length is 0\n");
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}
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if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
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panic("Instruction and data cache line lengths differ\n");
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}
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void cache_init(void)
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{
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read_decode_cache_bcr();
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if (is_isa_arcv2())
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read_decode_cache_bcr_arcv2();
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if (is_isa_arcv2() && ioc_enabled())
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arc_ioc_setup();
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if (is_isa_arcv2() && slc_exists())
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slc_upper_region_init();
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}
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int icache_status(void)
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{
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return icache_enabled();
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}
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void icache_enable(void)
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{
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if (icache_exists())
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
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~IC_CTRL_CACHE_DISABLE);
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}
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void icache_disable(void)
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{
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if (!icache_exists())
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return;
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__ic_entire_invalidate();
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
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IC_CTRL_CACHE_DISABLE);
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}
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/* IC supports only invalidation */
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static inlined_cachefunc void __ic_entire_invalidate(void)
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{
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if (!icache_enabled())
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return;
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/* Any write to IC_IVIC register triggers invalidation of entire I$ */
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write_aux_reg(ARC_AUX_IC_IVIC, 1);
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/*
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* As per ARC HS databook (see chapter 5.3.3.2)
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* it is required to add 3 NOPs after each write to IC_IVIC.
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*/
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|
__builtin_arc_nop();
|
|
__builtin_arc_nop();
|
|
__builtin_arc_nop();
|
|
read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
|
|
}
|
|
|
|
void invalidate_icache_all(void)
|
|
{
|
|
__ic_entire_invalidate();
|
|
|
|
/*
|
|
* If SL$ is bypassed for data it is used only for instructions,
|
|
* so we need to invalidate it too.
|
|
* TODO: HS 3.0 supports SLC disable so we need to check slc
|
|
* enable/disable status here.
|
|
*/
|
|
if (is_isa_arcv2() && slc_data_bypass())
|
|
__slc_entire_op(OP_INV);
|
|
}
|
|
|
|
int dcache_status(void)
|
|
{
|
|
return dcache_enabled();
|
|
}
|
|
|
|
void dcache_enable(void)
|
|
{
|
|
if (!dcache_exists())
|
|
return;
|
|
|
|
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
|
|
~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
|
|
}
|
|
|
|
void dcache_disable(void)
|
|
{
|
|
if (!dcache_exists())
|
|
return;
|
|
|
|
__dc_entire_op(OP_FLUSH_N_INV);
|
|
|
|
/*
|
|
* As SLC will be bypassed for data after L1 D$ disable we need to
|
|
* flush it first before L1 D$ disable. Also we invalidate SLC to
|
|
* avoid any inconsistent data problems after enabling L1 D$ again with
|
|
* dcache_enable function.
|
|
*/
|
|
if (is_isa_arcv2())
|
|
__slc_entire_op(OP_FLUSH_N_INV);
|
|
|
|
write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
|
|
DC_CTRL_CACHE_DISABLE);
|
|
}
|
|
|
|
/* Common Helper for Line Operations on D-cache */
|
|
static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz,
|
|
const int cacheop)
|
|
{
|
|
unsigned int aux_cmd;
|
|
int num_lines;
|
|
|
|
/* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
|
|
aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
|
|
|
|
sz += paddr & ~CACHE_LINE_MASK;
|
|
paddr &= CACHE_LINE_MASK;
|
|
|
|
num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz);
|
|
|
|
while (num_lines-- > 0) {
|
|
#if (CONFIG_ARC_MMU_VER == 3)
|
|
write_aux_reg(ARC_AUX_DC_PTAG, paddr);
|
|
#endif
|
|
write_aux_reg(aux_cmd, paddr);
|
|
paddr += gd->arch.l1_line_sz;
|
|
}
|
|
}
|
|
|
|
static inlined_cachefunc void __before_dc_op(const int op)
|
|
{
|
|
unsigned int ctrl;
|
|
|
|
ctrl = read_aux_reg(ARC_AUX_DC_CTRL);
|
|
|
|
/* IM bit implies flush-n-inv, instead of vanilla inv */
|
|
if (op == OP_INV)
|
|
ctrl &= ~DC_CTRL_INV_MODE_FLUSH;
|
|
else
|
|
ctrl |= DC_CTRL_INV_MODE_FLUSH;
|
|
|
|
write_aux_reg(ARC_AUX_DC_CTRL, ctrl);
|
|
}
|
|
|
|
static inlined_cachefunc void __after_dc_op(const int op)
|
|
{
|
|
if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
|
|
while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
|
|
}
|
|
|
|
static inlined_cachefunc void __dc_entire_op(const int cacheop)
|
|
{
|
|
int aux;
|
|
|
|
if (!dcache_enabled())
|
|
return;
|
|
|
|
__before_dc_op(cacheop);
|
|
|
|
if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
|
|
aux = ARC_AUX_DC_IVDC;
|
|
else
|
|
aux = ARC_AUX_DC_FLSH;
|
|
|
|
write_aux_reg(aux, 0x1);
|
|
|
|
__after_dc_op(cacheop);
|
|
}
|
|
|
|
static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
|
|
const int cacheop)
|
|
{
|
|
if (!dcache_enabled())
|
|
return;
|
|
|
|
__before_dc_op(cacheop);
|
|
__dcache_line_loop(paddr, sz, cacheop);
|
|
__after_dc_op(cacheop);
|
|
}
|
|
|
|
void invalidate_dcache_range(unsigned long start, unsigned long end)
|
|
{
|
|
if (start >= end)
|
|
return;
|
|
|
|
/*
|
|
* ARCv1 -> call __dc_line_op
|
|
* ARCv2 && L1 D$ disabled -> nothing
|
|
* ARCv2 && L1 D$ enabled && IOC enabled -> nothing
|
|
* ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
|
|
*/
|
|
if (!is_isa_arcv2() || !ioc_enabled())
|
|
__dc_line_op(start, end - start, OP_INV);
|
|
|
|
if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
|
|
__slc_rgn_op(start, end - start, OP_INV);
|
|
}
|
|
|
|
void flush_dcache_range(unsigned long start, unsigned long end)
|
|
{
|
|
if (start >= end)
|
|
return;
|
|
|
|
/*
|
|
* ARCv1 -> call __dc_line_op
|
|
* ARCv2 && L1 D$ disabled -> nothing
|
|
* ARCv2 && L1 D$ enabled && IOC enabled -> nothing
|
|
* ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
|
|
*/
|
|
if (!is_isa_arcv2() || !ioc_enabled())
|
|
__dc_line_op(start, end - start, OP_FLUSH);
|
|
|
|
if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
|
|
__slc_rgn_op(start, end - start, OP_FLUSH);
|
|
}
|
|
|
|
void flush_cache(unsigned long start, unsigned long size)
|
|
{
|
|
flush_dcache_range(start, start + size);
|
|
}
|
|
|
|
/*
|
|
* As invalidate_dcache_all() is not used in generic U-Boot code and as we
|
|
* don't need it in arch/arc code alone (invalidate without flush) we implement
|
|
* flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because
|
|
* it's much safer. See [ NOTE 1 ] for more details.
|
|
*/
|
|
void flush_n_invalidate_dcache_all(void)
|
|
{
|
|
__dc_entire_op(OP_FLUSH_N_INV);
|
|
|
|
if (is_isa_arcv2() && !slc_data_bypass())
|
|
__slc_entire_op(OP_FLUSH_N_INV);
|
|
}
|
|
|
|
void flush_dcache_all(void)
|
|
{
|
|
__dc_entire_op(OP_FLUSH);
|
|
|
|
if (is_isa_arcv2() && !slc_data_bypass())
|
|
__slc_entire_op(OP_FLUSH);
|
|
}
|
|
|
|
/*
|
|
* This is function to cleanup all caches (and therefore sync I/D caches) which
|
|
* can be used for cleanup before linux launch or to sync caches during
|
|
* relocation.
|
|
*/
|
|
void sync_n_cleanup_cache_all(void)
|
|
{
|
|
__dc_entire_op(OP_FLUSH_N_INV);
|
|
|
|
/*
|
|
* If SL$ is bypassed for data it is used only for instructions,
|
|
* and we shouldn't flush it. So invalidate it instead of flush_n_inv.
|
|
*/
|
|
if (is_isa_arcv2()) {
|
|
if (slc_data_bypass())
|
|
__slc_entire_op(OP_INV);
|
|
else
|
|
__slc_entire_op(OP_FLUSH_N_INV);
|
|
}
|
|
|
|
__ic_entire_invalidate();
|
|
}
|