mirror of
https://github.com/AsahiLinux/u-boot
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680c613a5c
fixes breakeage introduced by commit
a37c36f4e7 "powerpc/8xxx: query
feature reporting register for num cores on unknown cpus"
Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
110 lines
3.1 KiB
C
110 lines
3.1 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 (440 port)
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* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
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*
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* (C) Copyright 2003 Motorola Inc. (MPC85xx port)
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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int interrupt_init_cpu(unsigned int *decrementer_count)
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{
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ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
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out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
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while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
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;
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out_be32(&pic->gcr, MPC85xx_PICGCR_M);
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in_be32(&pic->gcr);
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*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
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/* PIE is same as DIE, dec interrupt enable */
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mtspr(SPRN_TCR, TCR_PIE);
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#ifdef CONFIG_INTERRUPTS
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pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
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debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
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pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
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debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
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pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
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debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
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#ifdef CONFIG_PCI1
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pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
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debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
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#endif
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#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
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pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
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debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
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#endif
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#ifdef CONFIG_PCIE1
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pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
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debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
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#endif
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#ifdef CONFIG_PCIE3
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pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
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debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
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#endif
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pic->ctpr=0; /* 40080 clear current task priority register */
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#endif
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return (0);
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}
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/* Install and free a interrupt handler. Not implemented yet. */
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void
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irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
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{
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return;
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}
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void
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irq_free_handler(int vec)
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{
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return;
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}
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void timer_interrupt_cpu(struct pt_regs *regs)
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{
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/* PIS is same as DIS, dec interrupt status */
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mtspr(SPRN_TSR, TSR_PIS);
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}
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#if defined(CONFIG_CMD_IRQ)
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/* irqinfo - print information about PCI devices,not implemented. */
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int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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return 0;
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}
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#endif
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