u-boot/board/freescale/c29xpcie
Tom Rini a09fea1d28 env: Finish migration of common ENV options
- In ARMv8 NXP Layerscape platforms we also need to make use of
  CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so.
- On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define
  to 0.
- Add Kconfig entry for ENV_ADDR.
- Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it.
- Add ENV_xxx_REDUND options that depend on their primary option and
  SYS_REDUNDAND_ENVIRONMENT
- On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR
  for the pre-main-U-Boot environment location.
- On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but
  rather it being non-zero, as it will now be zero by default.
- Rework the env_offset absolute in env/embedded.o to not use
  CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within
  ENV_IS_IN_FLASH.
- Migrate all platforms.

Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: uboot-stm32@st-md-mailman.stormreply.com
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-20 18:32:09 -05:00
..
c29xpcie.c env: Move env_get() to env.h 2019-08-11 16:43:41 -04:00
cpld.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
cpld.h SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
ddr.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
Kconfig NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST 2017-01-24 10:33:59 -05:00
law.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
MAINTAINERS MAINTAINERS: Switch nxp.com domain 2018-05-01 22:38:10 -04:00
Makefile SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
README Use correct spelling of "U-Boot" 2016-02-06 12:00:59 +01:00
spl.c env: Finish migration of common ENV options 2019-11-20 18:32:09 -05:00
spl_minimal.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
tlb.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00

Overview
=========
C29XPCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module.
It includes C293PCIE board, C293PCIE board and C291PCIE board.
The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engines.
(maximum core frequency 1000/1200 MHz).

The C29xPCIE board features are as follows:
Memory subsystem:
	- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
	- 64 Mbyte NOR flash single-chip memory
	- 4 Gbyte NAND flash memory
	- 1 Mbit AT24C1024 I2C EEPROM
	- 16 Mbyte SPI memory

Interfaces:
	- 10/100/1000 BaseT Ethernet ports:
		- eTSEC1, RGMII: one 10/100/1000 port
		- eTSEC2, RGMII: one 10/100/1000 port
	- DUART interface:
		- DUART interface: supports two UARTs up to 115200 bps for
		   console display

Board connectors:
	- Mini-ITX power supply connector
	- JTAG/COP for debugging

Physical Memory Map on C29xPCIE
===============================
Address Start   Address End   Memory type
0x0_0000_0000 - 0x0_1fff_ffff   512MB DDR
0xc_0000_0000 - 0xc_8fff_ffff   256MB PCIE memory
0xf_ec00_0000 - 0xf_efff_ffff   64MB NOR flash
0xf_ffb0_0000 - 0xf_ffb7_ffff   512KB SRAM
0xf_ffc0_0000 - 0xf_ffc0_ffff   64KB PCIE IO
0xf_ffdf_0000 - 0xf_ffdf_0fff   4KB CPLD
0xf_ffe0_0000 - 0xf_ffef_ffff   1MB CCSR

Serial Port Configuration on C29xPCIE
=====================================
Configure the serial port of the attached computer with the following values:
	-Data rate: 115200 bps
	-Number of data bits: 8
	-Parity: None
	-Number of Stop bits: 1
	-Flow Control: Hardware/None

Settings of DIP-switch
======================
  SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
  SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
Note: 1 stands for 'off', 0 stands for 'on'

Build and program U-Boot to NOR flash
==================================
1. Build u-boot.bin image example:
	export ARCH=powerpc
	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
	make C293PCIE

2. Program u-boot.bin into NOR flash
	=> tftp $loadaddr $uboot
	=> protect off eff40000 +$filesize
	=> erase eff40000 +$filesize
	=> cp.b $loadaddr eff40000 $filesize

3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.

Alternate NOR bank
==================
There are four banks in C29XPCIE board, example to change bank booting:
1. Program u-boot.bin into alternate NOR bank
	=> tftp $loadaddr $uboot
	=> protect off e9f40000 +$filesize
	=> erase e9f40000 +$filesize
	=> cp.b $loadaddr e9f40000 $filesize

2. Switch to alternate NOR bank
	=> cpld_cmd reset altbank [bank]
	- [bank] bank value select 1-4
	- bank 1 on the flash 0x0000000~0x0ffffff
	- bank 2 on the flash 0x1000000~0x1ffffff
	- bank 3 on the flash 0x2000000~0x2ffffff
	- bank 4 on the flash 0x3000000~0x3ffffff
	or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.

Build and program U-Boot to SPI flash
==================================
1. Build u-boot-spi.bin image
	make C29xPCIE_SPIFLASH_config; make
	Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.

2. Program u-boot-spi.bin into SPI flash
	=> tftp $loadaddr $uboot-spi
	=> sf erase 0 100000
	=> sf write $loadaddr 0 $filesize

3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.