mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 01:17:39 +00:00
679530c3c6
The subdivision name "TQ Components" hasn't been in use for a long time. Rename the vendor directory to "tq", which also matches our Device Tree vendor prefix. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
124 lines
4.1 KiB
INI
124 lines
4.1 KiB
INI
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
|
|
*
|
|
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
|
|
* and create imximage boot image
|
|
*
|
|
* The syntax is taken as close as possible with the kwbimage
|
|
*/
|
|
|
|
/* image version */
|
|
IMAGE_VERSION 2
|
|
|
|
#define __ASSEMBLY__
|
|
#include <config.h>
|
|
|
|
/*
|
|
* Boot Device : one of
|
|
* spi, sd (the board has no nand neither onenand)
|
|
*/
|
|
#if defined(CONFIG_TQMA6X_MMC_BOOT)
|
|
BOOT_FROM sd
|
|
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
|
|
BOOT_FROM spi
|
|
#endif
|
|
|
|
#include "asm/arch/mx6-ddr.h"
|
|
#include "asm/arch/iomux.h"
|
|
#include "asm/arch/crm_regs.h"
|
|
|
|
/* TQMa6S DDR config Rev. 0100B */
|
|
/* IOMUX configuration */
|
|
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
|
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000
|
|
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
|
|
DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
|
|
DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
|
|
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
|
|
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
|
|
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
|
|
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
|
|
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
|
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
|
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
|
|
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
|
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
|
|
DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
|
|
DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
|
|
DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
|
|
|
|
/* memory interface calibration values */
|
|
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
|
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000
|
|
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000
|
|
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000
|
|
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A
|
|
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000
|
|
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32
|
|
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000
|
|
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000
|
|
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
|
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000
|
|
|
|
/* configure memory interface */
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
|
|
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
|
|
DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
|
|
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
|
|
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
|
DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
|
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
|
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
|
|
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
|
|
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
|
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
|
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
|
|
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
|
|
DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
|
|
|
#include "clocks.cfg"
|